1Spartan-3 FPGA Family
Data Sheet
Product Specification
DS099 June 27, 2013
Module 1:
Introduction and Ordering Information
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IntroductionFeatures
Architectural OverviewArray Sizes and ResourcesUser I/O ChartOrdering Information
Module 4: Pinout Descriptions
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Pin Descriptions?
Pin Behavior During ConfigurationPackage OverviewPinout Tables?
Footprints
Module 2: Functional Description
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Input/Output Blocks (IOBs)?????
IOB Overview
SelectIO? Interface I/O Standards
Configurable Logic Blocks (CLBs)Block RAMDedicated Multipliers
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Digital Clock Manager (DCM)Clock NetworkConfiguration
Module 3:
DC and Switching Characteristics
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DC Electrical Characteristics?????
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Absolute Maximum RatingsSupply Voltage SpecificationsRecommended Operating ConditionsDC CharacteristicsI/O Timing
Internal Logic TimingDCM Timing
Configuration and JTAG Timing
Switching Characteristics
DS099 June 27, 2013Product Specification
Spartan-3 FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3 family architecture consists of five fundamental programmable functional elements:?
Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storageelements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logicalfunctions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOBsupports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight
high-performance differential standards, are available as shown in Table2. Double Data-Rate (DDR) registers areincluded. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying boarddesigns.
Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying,dividing, and phase shifting clock signals.
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These elements are organized as shown in Figure1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several 18-Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outerblock RAM columns.
The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements,
transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.
X-Ref Target - Figure 1DS099-1_01_032703Notes:
1.
The two additional block RAM columns of the XC3S4000 and XC3S5000 devicesare shown with dashed lines. The XC3S50 has only the block RAM column on thefar left.
Figure 1:Spartan-3 Family Architecture
Configuration
Spartan-3 FPGAs are programmed by loading configuration data into robust reprogrammable static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA,
configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
The output frequency (fCLKFX) can be expressed as a function of the incoming clock frequency (fCLKIN) as follows:
fCLKFX = fCLKIN(CLKFX_MULTIPLY/CLKFX_DIVIDE)
Equation3
Regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met:??
The two values fall within their corresponding ranges, as specified in Table18.
The fCLKFX frequency calculated from the above expression accords with the DCM’s operating frequencyspecifications.
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, then the frequency of the output clock signal would be 5/3 that of the input clock signal.
DFS Frequency Modes
The DFS supports two operating modes, High Frequency and Low Frequency, with each specified over a different clock frequency range. The DFS_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set to LOW, the Low Frequency mode permits the two DFS outputs to operate over a low-to-moderate frequency range. When the attribute is set to HIGH, the High Frequency mode allows both these outputs to operate at the highest possible frequencies.
DFS With or Without the DLL
The DFS component can be used with or without the DLL component:
Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the respective CLKFX_MULTIPLY and CLKFX_DIVIDE values, generating a clock with the new target frequency on the CLKFX and CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS component. This case does not employ feedback loop; therefore, it cannot correct for clock distribution delay.
With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the clock distribution delay. In this case, a feedback loop from the CLK0 output to the CLKFB input must be present.
The DLL and DFS components work together to achieve this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL selects the delay element for which the output clock edge coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input and output clock edges will coincide every three input periods, which is equivalent in time to five output periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values achieve faster lock times. With no factors common to the two attributes, alignment will occur once with every number of cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factoring wherever possible. For example, given CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. While both value-pairs will result in the multiplication of clock frequency by 3/2, the latter value-pair will enable the DLL to lock more quickly.
Table 18:DFS Attributes
Attribute
DFS_FREQUENCY_MODECLKFX_MULTIPLYCLKFX_DIVIDE
Frequency multiplier constantFrequency divisor constant
Description
Chooses between High Frequency and Low Frequency modes
Values
Low, High
Integer from 2 to 32Integer from 1 to 32
Table 19:DFS Signals
SignalCLKFXCLKFX180
DirectionOutputOutput
Description
Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/CLKFX_DIVIDE) to generate a clock signal with a new target frequency.
Generates a clock signal with same frequency as CLKFX, only shifted 180° out-of-phase.
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S150E-6FG456I中文规格书 - 图文
