technologies in those markets is often linked to the availability of devices in those technologies, not the complexity of the application itself. The complexity can be handled in many cases by an 8-bit microcontroller, or 32-bit for high-end applications. Products such as the 0.35 μm I3T are able to manage the integration at a reasonable cost. A typical application diagram of a real mixed-signal SoC is shown in Figure 1.9. Basically,
the
chip
integrates
the
system
functionality from the sensor to the actuator, going through some digital processing. Conventional mixed-signal technology allows analog control and signal processing functions such as amplifiers, analog-to-digital converters (ADCs) and filters to be
combined with digital functionality such as microcontrollers, memory, timers and logic control functions on a single, customized chip. All signals that process an algorithm or arithmetic calculation are digital, so conversion of analog to digital signals is mandatory when submitting data for comparison or processing by via a microcontroller, while conversion from digital output signals to analog high-voltage signals is required to drive an actuator or a load. The most recent mixed-signal technology AMIS developed, significantly simplifies the implementation of such driver functionality by allowing much higher voltage functionality to be integrated into an IC alongside the relatively low voltages required for conventional mixed-signal functions. This high-voltage mixed-signal technology is particularly relevant to automotive electronics applications where higher voltage outputs — to drive a motor or actuate a relay — need to be combined with analog signal conditioning functions and complex digital processing.
A growing trend in mixed-signal circuit design is to add some type of central processing circuit to the analog circuits. For many applications the suitable choice of processing intelligence is an 8-bit microcontroller core such as an 8051 or 6502. 8 bits remains the most popular choice as this type of SoC is not intended to replace complex high-end central microcontrollers but more decentralized or slave applications such as sensor conditioning circuitry with local (as close to the sensor as possible) simple intelligence to control relays or motors. An automotive example
Figure 1.9 Mixed-signal SoC diagram
would be the lateral actuation of a car’s headlamps when the steering wheel is turned to improve the driver’s safety and improve field of vision. The sensor input would come from the steering angle via a serial link (most of the time with a LIN or I2C protocol) and the SoC would be close to the motor with an on-board set of algorithms to command the motor’s movement.
For higher end applications that require more calculation power, the move to ARM processors is possible. This creates a high-end solution (up to date for the mature markets) which could last over the application’s lifespan because the microcontroller would be a small part of an integrated circuit that emulates the module’s functionalities.
In order to understand how larger geometries can be better suited for some mixed-signal applications, one needs to understand all of the characteristics involved. Below we will discuss seven key characteristics, however this is by no means comprehensive.
Gate and memory size in mixed-signal applications generally drive cost.
Gate and memory size drive cost because most mixed-signal devices are core limited. This can be quite different than an all-digital circuit. Many times, the all-digital device will have so many I/Os that the number of pads on the device determines the periphery and therefore the area. This is rarely the case for mixed-signal devices. For the most part digital cells scale pretty closely to the expected area savings. One would expect a 0.25-micron cell to be 51 percent smaller than a 0.35-micron cell of equivalent function. This is illustrated by the following formula:
(0.25)20.0625Size Ratio ???51%
(0.35)20.1225While this holds for digital cells we will see that analog cells are quite a different story. Therefore the amount of digital content (including memory) is the key in determining the best technology for the application.
2. Parasitic lessens as the geometry decreases.
This is good news for both the digital and analog designer. Understandably this will translate into high bandwidths and data rates. While the magnitude of the parasitic
capacitance per gate or resistance of the interconnection is most assuredly lower as geometry decreases, it is also less predictable. This can cause analog modeling problems and highlights the need for careful understanding of the parasitic.
3. The trans-conductance characteristic is the relationship between a drain current and the voltage across the gate and source.
As the geometry decreases the trans-conductance gets higher. This is good news for both analog and digital domains in that smaller conductance interacts with capacitance to create smaller bandwidths and therefore lower data rates.
It is well understood that as geometry decreases the voltage limits of the device decrease as well. In the pure digital world this is beneficial in several ways: less power and less radiated emissions. The only downside is the need for multiple voltage rails on most digital circuits. In the analog domain, the power savings is there but reduced range of operation makes the design task harder. It is quite common for analog designers to bias their circuits at VT + 2Von and Vdd ? (VT + 2Von). Unfortunately, the threshold voltage, VT, does not scale with the geometry. In other words, the operating range of voltages gets smaller as the technology shrinks. This means the analog portions of a circuit must be more tightly controlled which translates to larger, better matched transistors.
4. Channel resistance gets lower as the technology shrinks.
While this may sound like a good thing, and for digital circuits it generally is, this translates to transistors with lower gain in the analog domain. Lower gain may mean more stages in the circuit.
5. The linearity of smaller geometries also becomes a factor in analog designs.
Often non-linearity problems are solved by increasing the size of the circuit. An example of this can be seen in D/A and A/D converters where the performance of the converter is very much proportional to the size of the circuit.
6. Noise in circuits implemented in smaller technologies can cause
problems for analog designers.
This is usually worsened by the fact that there is usually a large and fast digital circuit that is generating much of the noise. The smaller operating voltage range works against the designer as well. Signal to noise ratio in the analog circuit gets worse because the signal levels go down but the noise levels may actually go up.
7. Analog circuit modeling in smaller geometries is problematic.
Much of this is due to the lower levels of predictability and the nature of the parasitic. Some of it is due to the maturity of the technology as well. This, of course, will improve as the technology develops.
Because of these items listed above it is important to understand that as the process geometry shrinks, the analog actually gets bigger, and definitely harder. This has to be compensated by increasing the sizes of the transistors, capacitors and resistors used. Moving to smaller technologies should only be done when the performance requirements of the application demand it. For most mixed-signal SoC devices this will be driven by the digital gate count and the amount of memory in the design. Only when there is significant digital content should you consider smaller technologies.
Conclusion
The latest generation of mixed-signal process technologies has moved well into the deep sub-micron world where adding digital circuits and cores to an analog ASIC has become a cost-effective approach.
With the addition of digital process capability and the digital processing horsepower that becomes available, many analog functions are being converted to digital signals earlier in the signal path. The advantage of this approach is that digital filters and digital control elements are not sensitive to drift inaccuracies caused by aging, process changes or temperature changes. The result is a much more robust design than an analog-only approach.
中文译文：
桥接模拟与数字世界之间的鸿沟
大多数应用程序要求模拟和数字功能的并存，把此功能结合在单一芯片上的好处是很明显的。然而，这样的混合信号集成也向人们提出了重大挑战。此外，数字和模拟功能往往以不同的速度进行发展，但混合信号在如工业，汽车和医疗行业的解决方案在关键时期必须保持是能用的。最新的混合信号半导体工艺正在着力解决这些问题，本文将着重于当具体指定集成混合信号解决方案时设计者应考虑的一些问题。
在现实世界中混合信号的解决方案
系统设计人员经常从一个给定设计的模拟区域中进行数字区域的分区，这样做有多种原因：这两种技术混合组件的可用性，数字化设计的复杂性或作为标准产品的纯数字处理部分的存在。在集成电路里配置模拟器件确实能让系统设计师降低整个模块的成本。
此集成方法在诸如信或计算机等先进领域通常是难以实现的，但对于更成熟的或传统的市场，如汽车，医疗和工业是有实际意义的。对于这些成熟市场的大部分应用，数字化功能研究者正在寻找曾是纯模拟设计的方法。添加数字功能到模拟设计，部分上帮助了开发新的工艺技术，该工艺可以处理短信道，快速转换数字晶体管和高电压模拟晶体管。例如，AMI半导体公司最新的混合信号技术提供了在相同的设计平台上的数字和模拟集成功能。 I3T技术系列是基于0.35微米的补充金属氧化物半导体(晶体管型)的。有些人认为从一个纯粹的数字设计师的角度来看，这项技术已经过时，但它却是处在汽车，工业和医疗行业的最前沿的技术。
这种可选特性使真正的片上系统的设计能实现以下功能，包括高电压接口可达80伏，微处理性能可达32位，无线性能可达2.8千兆/赫兹，以及复杂逻辑设
基于multisim及锁相环的2PSK2ASK2FSK的调制解调电路仿真毕业设计
