Device/Package Combinations and Maximum I/Os
Table1-1 shows the maximum number of user I/Os possible in Virtex-5 FPGA flip-chip packages. FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
Table 1-1:
Flip-Chip Packages
Packages
FF3241.0019 x 19220
FF6651.0027 x 27360
FF6761.0027 x 27440
FF1136FF11531.0035 x 35640
1.0035 x 35800
FF11561.0035 x 35360
FF17381.0042.5 x 42.5960
FF17591.0042.5 x 42.5680
FF17601.0042.5 x 42.51200
Package
SpecificationsFF323Pitch(mm)Size(mm)Maximum I/Os
1.0019 x 19172
The number of I/Os per package includes all user I/Os except the 19 pins listed in Table1-2.
Table 1-2:Virtex-5 FPGA I/O Pinsin the Dedicated Configuration Bank (Bank0)DXPDXNVBATTPROGRAM_B
HSWAPEND_INDONECCLK_0
INIT_B_0CS_B_0RDWR_B_0TCK_0
M0_0M1_0M2_0TMS
TDI
D_OUT_BUSYTDO_0
The RocketIO? GTP transceiver I/O channels for the devices listed in Table1-3 or the GTX transceiver I/O channels for the devices listed in Table1-4.
Table 1-3:I/O ChannelsMGTRXPMGTRXNMGTTXPMGTTXN
Notes:
1.The XC5VLX30T has 4 GTP I/O channels in the FF323/FFG323 package and 8 GTP I/O channels in the FF665/FFG665 package.2.The XC5VLX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package. 3.The XC5VSX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package.
Number of GTP Transceiver I/O Channels/Device
Device
LX20TLX30T(1)SX35TLX50T(2)SX50T(3)LX85TSX95TLX110TLX155TLX220TSX240TLX330T
4444
4 or 84 or 84 or 84 or 8
8888
8 or 128 or 128 or 128 or 12
8 or 128 or 128 or 128 or 12
12121212
16161616
16161616
16161616
16161616
24242424
24242424
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Virtex-5 FPGA Packaging and Pinout Specification
FF1153 Package—LX50, LX85, LX110, and LX155
Table 2-6:FF1153 Package—LX50, LX85, LX110, and LX155 (Continued)
Bank
Pin Description
Pin Number
AK22AK23AJ16AH17AJ17AK16AL23AK24AK17AK18AL20AL21AG18AH18AL18AL19AK13AK12AL15AL16AK11AL11AL13AL14B32A33B33C33C32D32C34D34G32
No Connect (NC)
666666666666666666666666111111111111111111
IO_L8P_CC_6 IO_L8N_CC_6(2)IO_L9P_CC_6 IO_L9N_CC_6(2)IO_L10P_CC_6 IO_L10N_CC_6(2)IO_L11P_CC_6 IO_L11N_CC_6(2)IO_L12P_VRN_6 IO_L12N_VRP_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_VREF_6
IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L0P_11 IO_L0N_11 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11
LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85LX50, LX85
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 4:Mechanical Drawings
FF323 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm Pitch)
X-Ref Target - Figure 4-1ug195_c4_10_032508Figure 4-1: FF323 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 4:Mechanical Drawings
EF1136 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm Pitch)
X-Ref Target - Figure 4-5ug195_c4_20_100909Figure 4-5:EF1136 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-5 FPGA Packaging and Pinout Specification
FPGA可编程逻辑器件芯片XCZU17EG-1FFVB1517E中文规格书 - 图文
