The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5gigatransfers per second (GT/s) for a Gen1 application and 5.0GT/s for a Gen2 application. The PCIe transmit and receive signal datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7series FPGAs GTX transceivers are used for multi-gigabit per second serial interfaces.
The XC7VX485T-2FFG1761C FPGA (-2 speed grade) included with the VC707 board supports up to Gen2 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin AB8, and the _N net is connected to pin AB7. The PCI Express clock circuit is shown in Figure1-14.
X-Ref Target - Figure 1-14P1PCI ExpressEight-LaneEdge connectorOEGNDREFCLK+REFCLK-GNDA12A13A14A15GNDPCIE_CLK_Q0_C_PPCIE_CLK_Q0_C_NC5440.01μF 25VX7RPCIE_CLK_Q0_PPCIE_CLK_Q0_NC5450.01μF 25VX7RUG885_c1_14_020612Figure 1-14:PCI Express Clock
PCIe lane width/size is selected through jumper J49 (Figure1-15). The default lane size selection is 1-lane (J49 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-15PCIE_PRSNT_X1PCIE_PRSNT_X4PCIE_PRSNT_X8135J49246PCIE_PRSNT_BUG885_c1_15_020612Figure 1-15:PCI Express Lane Size Select Jumper J49
Table1-12 lists the PCIe edge connector connections at P1.
Table 1-12:
Net NamePCIE_RX0_PPCIE_RX0_NPCIE_RX1_PPCIE_RX1_NPCIE_RX2_PPCIE_RX2_NPCIE_RX3_P
PCIe Edge Connector Connections GTX Quad 115
FPGA (U1)PCIe Edge Connector (P1)
PinPinName
Y4Y3AA6AA5AB4AB3AC6
B14B15B19B20B23B24B27
PETp0PETn0PETp1PETn1PETp2PETn2PETp3
Function
Integrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pairIntegrated Endpoint block receive pair
FHG1761
Placement
GTXE2_CHANNEL_X1Y11GTXE2_CHANNEL_X1Y11GTXE2_CHANNEL_X1Y10GTXE2_CHANNEL_X1Y10GTXE2_CHANNEL_X1Y9GTXE2_CHANNEL_X1Y9GTXE2_CHANNEL_X1Y8
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
SGMII GTX Transceiver Clock Generation
[Figure1-2, callout 16]
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX
transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling capacitors are present to allow the clock input of the FPGA to set the common mode voltage. Figure1-17 shows the Ethernet SGMII clock source.
X-Ref Target - Figure 1-17C30018pF 50VNPOVDDA_SGMIICLKVDD_SGMIICLKU2X325.00 MHz1X11SGMIICLK_XTAL_OUT3ICS844021I-01Clock GeneratorOEVDDAXTAL_OUTVDDQ0587SGMIICLK_Q0_C_PR3201.0MΩ 5?0118pF 50VNPO2GND2C280.1μF 25VX5RSGMIICLK_Q0_P4GND2X23SGMIICLK_XTAL_IN42XTAL_INGNDNQ06SGMIICLK_Q0_C_NSGMIICLK_Q0_NC290.1μF 25VX5RUG885_c1_17_020612GND_SGMIICLKGND_SGMIICLKGND_SGMIICLKFigure 1-17:Ethernet 125 MHz SGMII GTX Clock
References
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051) [Ref9] and in the LogiCORE IP Tri-Mode Ethernet MAC v4.5 User Guide (UG138) [Ref13].
The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the Marvell website [Ref21].
The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell website [Ref21].
For more information about the ICS844021 device, go to the Integrated Device Technology website [Ref22] and search for part number ICS844021.
USB-to-UART Bridge
[Figure1-2, callout 17]
The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707 Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the VC707 board.
Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm) that runs on the host computer. The VCP device
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
drivers must be installed on the host PC prior to establishing communications with the VC707 board.
The USB Connector Pin Assignments and Signal Definitions between J17 and U44 are listed in Table1-19.
Table 1-19:
USB Connector J17 Pin Assignments and Signal Definitions
Net Name
Description
CP2103GM (U44)Pin7843229
NameREGINVBUSD–D+GND1CNR_GND
USB Connector (J17)Pin1234
NameVBUSD_ND_PGND
USB_UART_VBUSUSB_D_NUSB_D_PUSB_UART_GND
+5V VBUS Powered
Bidirectional differential serial data (N-side)Bidirectional differential serial data (P-side)Signal ground
Table1-20 shows the USB connections between the FPGA and the UART.
Table 1-20:
FPGA to UART Connections
FPGA (U1)
PinAR34AT32AU36AU33
FunctionRTSCTSTXRX
DirectionOutputInputOutputInput
IOSTANDARDLVCMOS18LVCMOS18LVCMOS18LVCMOS18
Schematic Net
NameUSB_CTSUSB_RTSUSB_RXUSB_TX
CP2013 Device (U12)
Pin22232425
FunctionCTSRTSRXDTXD
DirectionInputOutputInputOutput
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref20].
HDMI Video Output
[Figure1-2, callout 18]
The VC707 board provides a High-Definition Multimedia Interface (HDMI?) video output using the Analog Devices ADV7511KSTZ-P HDMI transmitter (U48). The HDMI output is provided on a Molex 500254-1927 HDMI type-A connector (P2). The ADV7511 is wired to support 1080P 60Hz YCbCr and RGB video modes through 36-bit input data mapping.The VC707 board supports the following HDMI device interfaces:??????
36 data lines
Independent VSYNC, HSYNCSingle-ended input CLKInterrupt Out Pin to FPGAI2CSPDIF
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
FPGA可编程逻辑器件芯片XC2S30-6FG256I中文规格书 - 图文
