NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
CAUTIONIf level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.7.37.4APB interface
The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller.
7.37.5AHB multilayer matrix
The LPC408x/7x use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M4 to the flash memory, the main (32kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions.
7.37.6External interrupt inputs
The LPC408x/7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. The external interrupt input can optionally be used to wake up the processor from Power-down mode.
7.37.7Memory mapping control
The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M4 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC408x/7x is configured for 128 total interrupts.
7.38Debug control
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four watch points.
8. Limiting values
Table 7.Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]SymbolVDD(3V3)VDD(REG)(3V3)VDDAVi(VBAT)
LPC408X_7X
Parameter
supply voltage (3.3 V)
regulator supply voltage (3.3V)analog 3.3 V pad supply voltageinput voltage on pin VBAT
Conditionsexternal rail
Min?0.5?0.5?0.5
Max+4.6+4.6+4.6+4.6
UnitVVVV
for the RTC?0.5
All information provided in this document is subject to legal disclaimers.? NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheetRev. 3 — 11 January 2017 79 of 140
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Table 7.Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]SymbolVi(VREFP)VIAVI
Parameter
input voltage on pin VREFPanalog input voltageinput voltage
on ADC related pins
5V tolerant digital I/O pins; VDD(3V3)?2.4VVDD(3V3)?0 Vother I/O pins
IDDISSIlatch
supply currentground currentI/O latch-up current
per supply pinper ground pin?(0.5VDD(3V3)) < VI < (1.5VDD(3V3));Tj < 125?C
TstgPtot(pack)
storage temperature
total power dissipation (per package)
non-operatingbased on package heat transfer, not device power consumptionhuman body model; all pins
[5][4][2][3][2]
ConditionsMin?0.5?0.5?0.5
Max+4.6+5.1+5.5
UnitVVV
?0.5?0.5---
+3.6VDD(3V3) + 0.5100100100
VVmAmAmA
?65-
+1501.5
?CW
VESD
[1]
electrostatic discharge voltage-4000V
The following applies to the limiting values:
a)This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the ratedmaximum.b)Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2][3][4][5]
Including voltage on outputs in 3-state mode.Not to exceed 4.6V.
The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determinedbased on the required shelf lifetime. Please refer to the JEDEC spec for further details.
Human body model: equivalent to discharging a 100pF capacitor through a 1.5k? series resistor.
9.Thermal characteristics
The average chip junction temperature, Tj (?C), can be calculated using the following
equation:
Tj=Tamb+?PD?Rth?j–a??
(1)
?Tamb = ambient temperature (?C),
?Rth(j-a) = the package junction-to-ambient thermal resistance (?C/W)?PD = sum of internal and I/O power dissipation
LPC408X_7XAll information provided in this document is subject to legal disclaimers.? NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheetRev. 3 — 11 January 2017 80 of 140
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