Default Switch and Jumper Settings
GPIO DIP Switch SW2
See Figure1-2 Item 24 for location of SW2. Default settings are shown in FigureA-1 and details are listed in TableA-1.
X-Ref Target - Figure A-1ON Position = 112345678SW2OFF Position = 0UG885_aB_01_020612Figure A-1:SW2 Default Settings
Table A-1:
SW2 Default Switch Settings
FunctionGPIO_DIP_SW0GPIO_DIP_SW1GPIO_DIP_SW2GPIO_DIP_SW3GPIO_DIP_SW4GPIO_DIP_SW5GPIO_DIP_SW6GPIO_DIP_SW7
DefaultOffOffOffOffOffOffOffOff
Position
12345678
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Appendix A:Default Switch and Jumper Settings
Configuration DIP Switch SW11
See Figure1-2 Item 29 for location of SW11. Default settings are shown in FigureA-2 and details are listed in TableA-2.
X-Ref Target - Figure A-2A25A24M2M1M012345OFF Position = 0UG885_aB_02_020612ON Position = 1Figure A-2:SW11 Default Settings
The default mode setting M[2:0]=010 selects Master BPI configuration at board power-on.Table A-2:
Position
12345
SW11 Default Switch Settings
Function
FLASH_A25FLASH_A24FPGA_M2FPGA_M1FPGA_M0
A25A24M0M1M3
DefaultOffOffOffOnOff
Default Jumper Settings
See FigureA-3 for locations of jumpers listed in TableA-3.
Table A-3:Callout12345678910
Default Jumper SettingsJumperJ6J9J10J11J12J13J14J38J39J42
SFP Enable
XADC GND ferrite filter bypass jumperXADC GND-to-XADC_AGND jumperTI Controller U42 Addr 52 Reset jumperTI Controller U43 Addr 53 Reset jumperUSB Mini-B Connector J2 VBUS USB SMBC U8 CLKOUT selector
SFP RX Rate: 1-2=Full BW Rate, 2-3=Low BW RateSFP TX Rate: 1-2=Full BW Rate, 2-3=Low BW RateXADC external 1.2V or internal VREFP selector
Function
Schematic
Default Jumper
0381418 Page
Position
Number
NoneNone1–2NoneNoneNoneNone1–21–21–2
31404046504444313140
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
For external measurements an XADC header (J19) is provided. This header can be used to provide analog inputs to the FPGA's dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0],
VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.
A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure1-35 shows the XADC header connections.
X-Ref Target - Figure 1-35XADC_VNXADC_VAUX0PXADC_VCC5V0VADJXADC_VAUX8NXADC_DXPXADC_VREFXADC_GPIO_1XADC_GPIO_3135791113151719J192468101214161820XADC_VPXADC_VAUX0NXADC_VAUX8PXADC_DXNXADC_VCC_HEADERXADC_GPIO_0XADC_GPIO_2GNDXADC_AGNDXADC_AGNDUG885_c1_32_030512Figure 1-35:XADC Header (J19)
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
Configuration Options
The FPGA on the VC707 board can be configured by the following methods:??
Master BPI (uses the Linear BPI Flash).
JTAG (uses the USB-to-JTAG Bridge or Download cable). See USB JTAG for moreinformation
See 7SeriesFPGAs Configuration UserGuide (UG470) [Ref3] for further details on configuration modes.
The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0) settings selected through DIP switch SW11. Table1-34 lists the supported mode switch settings.Table 1-34:
Mode Switch SW11 Settings
Configuration Mode
Master BPIJTAG
Mode Pins (M2, M1, M0)
010101
Figure1-36 shows mode switch SW13.
X-Ref Target - Figure 1-36VCC2V5SW11FLASH_A25FLASH_A24FPGA_M2FPGA_M1FPGA_M0109876ON12345R401220Ω0.1 W1%R402220Ω0.1 W1%SDA05H1SBDR3961.21kΩ0.1 W1%R3971.21kΩ0.1 W1%R3981.21kΩ0.1 W1%R3991.21kΩ0.1 W1%R4001.21kΩ0.1 W1%GNDUG885_c1_33_030512Figure 1-36:Mode Switch
The mode pins settings on SW11 determine if the Linear BPI Flash is used for configuring the FPGA. DIP switch SW11 also provides the upper two address bits for the Linear BPI Flash and can be used to select one of multiple stored configuration bitstreams. Figure1-37 shows the connectivity between the onboard nonvolatile Flash devices used for configuration and the FPGA.
To obtain the fastest configuration speed an external 80MHz oscillator is wired to the EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA over the 16-bit datapath from the Linear BPI Flash memory at a maximum synchronous read rate of 80MHz.
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Configuration Options
X-Ref Target - Figure 1-37U1FPGASW9PROG_BVBATTTCKTMSBank 0TDI(VCCO = 1.8V)TDOVCCAUXIO (2.0V)U3P28F00AG18FE1Gb Flash MemoryRST_BCLKPart ofSW11ModeSwitchGNDD6BAS40-04M[2:0]1.8V261ΩDONE5 kΩB1GNDINIT_BCCLKWE_BOE_BADV_BFWE_BFOE_BADV_B3.3VDS10GREEN261Ω1.8VPart ofSW11RS1RS0A25A24Bank 15(VCCO = 1.8V)Q15NDS331N460 mWGNDGNDA27A[26:01]NCFLASH_A[25:0]NCA[26:25]A[23:16]A[15:00]D[15:00]D[15:00]Bank 14(VCCO = 1.8V)CE_BRDWR_BFCS_BWAIT(VCC, VCCQ, 1.8V)U40Oscillator80 MHzEMCCLKUG885_c1_34_030512Figure 1-37:VC707 Board Configuration Circuit
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
FPGA可编程逻辑器件芯片XQR5VFX130-1CN1752V中文规格书 - 图文
