AIIGX51002-2.0
This chapter describes the features of the logic array block (LAB) in the Arria?II core fabric. The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can configure to implement logic functions, arithmetic functions, and register functions.
This chapter contains the following sections:
■■
“Logic Array Blocks” on page2–1“Adaptive Logic Modules” on page2–5
Logic Array Blocks
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. The direct link interconnect allows the LAB to drive into the local interconnect of its left and right neighbors. Register chain connections transfer the output of the ALM register to the adjacent ALM register in the LAB. The Quartus? II Compiler places associated logic in the LAB or the adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency.
Figure2–1 shows the ArriaII LAB structure and the LAB interconnects.
Figure2–1.LAB Structure in ArriaII Devices
C4C12Row Interconnects ofVariable Speed & LengthR20R4ALMsDirect link
interconnect from adjacent block
Direct linkinterconnect fromadjacent block
Direct link
interconnect toadjacent block
Direct linkinterconnect toadjacent block
Local InterconnectLABMLABColumn Interconnects ofLocal Interconnect is Driven Variable Speed & Lengthfrom Either Side by Column Interconnect & LABs, & from Above by Row Interconnect
Arria II Device Handbook Volume 1: Device Interfaces and IntegrationDecember 2010
Chapter 5:Clock Networks and PLLs in Arria II DevicesPLLs in ArriaII Devices
Table5–21.Dynamic Phase-Shifting Control Signals for Arria II Devices(Part 1 of 2)
Signal Name
Description
Counter select. Four bits decoded to select either the M or one of the C counters for phase adjustment. One address maps to select all Ccounters. This signal is registered in the PLL on the rising edge of scanclk.
Selects dynamic phase shift direction;
1=UP;0=DOWN. Signal is registered in the PLL on the rising edge of scanclk.Logic high enables dynamic phase shifting.
Source
DestinationPLL
reconfiguration circuitPLL
reconfiguration circuitPLL
reconfiguration circuit
PHASECOUNTERSELECT[3:0]Logic array or I/O pins
PHASEUPDOWNLogic array or I/O pin Logic array or I/O pin
PHASESTEPArria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II Devices
PLLs in ArriaII Devices
Table5–21.Dynamic Phase-Shifting Control Signals for Arria II Devices(Part 2 of 2)
Signal Name
Description
Source
DestinationPLL
reconfiguration circuit
SCANCLKFree running clock from core used in
GCLK, RCLK, or combination with PHASESTEP to enable,
disable, or both dynamic phase shifting. Shared I/Opin with scanclk for dynamic reconfiguration.When asserted, this indicates to the core logic that the phase adjustment is complete and the PLL is ready to act on a possible second adjustment pulse. Asserts based on internal PLL timing. Deasserts on the rising edge of scanclk.
PLL
reconfiguration circuit
PHASEDONELogic array or I/O pins
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 6:I/O Features in Arria II Devices
I/O Standards Support
I/O Standards Support
Table6–1 lists the supported I/O standards for Arria II GX devices and the typical values for input and output VCCIO, VCCPD, VREF, and board VTT.
Table6–1.I/O Standards and Voltage Levels for Arria II GX Devices
Standard SupportJESD8-BJESD8-BJESD8-5JESD8-7JESD8-11JESD8-12PCI Rev 2.2PCI-X Rev 1.0JESD8-9BJESD8-15—JESD8-6JESD8-6JESD8-16AJESD8-9BJESD8-15—JESD8-6JESD8-6JESD8-16AANSI/TIA/EIA-644———
VCCIO (V)
I/O Standard
3.3-V LVTTL/3.3-V LVCMOS3.0-V LVTTL/3.0-V LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVCMOS1.2-V LVCMOS3.0-V PCI3.0-V PCI-X (1)SSTL-2 Class I, IISSTL-18 Class I, IISSTL-15 Class I HSTL-18 Class I, IIHSTL-15 Class I, IIHSTL-12 Class I, IIDifferential SSTL-2Differential SSTL-18Differential SSTL-15 Differential HSTL-18Differential HSTL-15Differential HSTL-12LVDS
RSDS and mini-LVDSLVPECLBLVDS
Notes to Table6–1:
Input Operation3.3/3.0/2.53.3/3.0/2.53.3/3.0/2.5 1.8/1.51.8/1.51.23.03.0 (2)(2)(2)(2)(2)(2)(2), (3)(2), (3)(2), (3)(2), (3)(2), (3)(2), (3)(2)—(2)(2)
Output Operation3.33.02.51.81.51.23.03.02.51.81.51.81.51.22.51.81.51.81.51.22.52.5—2.5
VCCPD (V) 3.33.02.52.52.52.53.03.02.52.52.52.52.52.52.52.52.52.52.52.52.52.52.52.5
VREF (V) VTT (V)
————————1.250.750.900.750.6——————————
————————1.250.750.900.750.61.250.900.750.900.750.60————
0.90 0.90 (1)PCI-X does not meet the PCI-X I-V curve requirement at the linear region.
(2)Single-ended SSTL/HSTL, differential SSTL/HSTL, LVDS, LVPECL, and BLVDS input buffers are powered by VCCPD.(3)Differential SSTL/HSTL inputs use LVDS differential input buffers without RD OCT support.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 6:I/O Features in Arria II DevicesI/O Standards Support
Table6–2 lists the supported I/O standards for Arria II GZ devices and the typical values for input and output VCCIO, VCCPD, VREF, and board VTT.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX190EF29C6G中文规格书 - 图文
