Pin NameVFS_0
DirectionInput
Description
e power supply pin for programming. When not used, connect to GND.
Dedicated System Monitor PinsAVDD_0(3)AVSS_0(3)VP_0(3)VN_0(3)VREFP_0(3)VREFN_ 0(3)
N/AN/AInputInputN/AN/A
System Monitor’s ADC analog positive supply voltage. Default connection is to VCCAUX.
System Monitor’s ADC analog ground reference. Default connection is to system GND via a ferrite bead.
System Monitor dedicated differential analog input (positive side).System Monitor dedicated differential analog input (negative side).1.25V reference input. Default connection is AVSS to enable the on-chip reference.
1.25V reference GND reference. Default connection is AVSS to enable the on-chip reference.
RocketIO Serial Transceiver Pins (GTXE1 and GTHE1_QUAD)MGTRXP[0:3]MGTRXN[0:3]MGTTXP[0:3]MGTTXN[0:3]MGTAVCCMGTAVCC_NMGTAVCC_SMGTAVTTMGTAVTT_NMGTAVTT_SMGTAVCC_LNMGTAVCC_LSMGTAVCC_RNMGTAVCC_RSMGTAVTT_LNMGTAVTT_LSMGTAVTT_RNMGTAVTT_RS
InputInputOutputOutputN/A
Positive differential receive port.Negative differential receive port.Positive differential transmit port.Negative differential transmit port.
Power-supply pin for GTXE1 transceiver’s mixed-signal circuitry and PLLs(4).Only available in Virtex-6 LXT and SXT devices.
Power-supply pin for GTXE1 transceiver’s TX and RX circuitry.(4).
N/A
Only available in Virtex-6 LXT and SXT devices.
Power-supply pin for transceiver mixed-signal circuitry left/north. Virtex-6 HXT devices only.
Power-supply pin for transceiver mixed-signal circuitry left/south. Virtex-6 HXT devices only.
Power-supply pin for transceiver mixed-signal circuitry right/north. Virtex-6 HXT devices only.
Power-supply pin for transceiver mixed-signal circuitry right/south. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry left/north. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry left/south. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry right/north. Virtex-6 HXT devices only.
Power-supply pin for TX and RX circuitry right/south. Virtex-6 HXT devices only.
N/AN/AN/AN/AN/AN/AN/AN/A
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T
Table 2-2:FF784/RF784 Package—LX75T, LX130T, LX195T, and LX240T (Cont’d)
Bank252525252626262626262626262626262626262626262626262626262626262626
Pin Description
Pin Number
H20G21F20F21E12D11E13E14H16G16G14F14J16H15B11C11D13D12C14B13J15K15B14A14F16F15G12F12E15D15A15A16A11
NoConnect (NC)
IO_L18P_GC_25IO_L18N_GC_25IO_L19P_GC_25IO_L19N_GC_25IO_L0P_26IO_L0N_26IO_L1P_26IO_L1N_26IO_L2P_26IO_L2N_26IO_L3P_26IO_L3N_26IO_L4P_26IO_L4N_VREF_26IO_L5P_26IO_L5N_26IO_L6P_26IO_L6N_26IO_L7P_26IO_L7N_26IO_L8P_SRCC_26IO_L8N_SRCC_26IO_L9P_MRCC_26IO_L9N_MRCC_26IO_L10P_MRCC_26IO_L10N_MRCC_26IO_L11P_SRCC_26IO_L11N_SRCC_26IO_L12P_VRN_26IO_L12N_VRP_26IO_L13P_26IO_L13N_26IO_L14P_26
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T, and SX475T
Table 2-5:FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T, and SX475T (Cont’d)
Bank2525252526262626262626262626262626262626262626262626262626262626
Pin Description
Pin Number
H28H29B31A31C20D20A23A24G21G22B23C23J20J21B21B22E22E23A20A21F19F20B20C19F21G20H19H20D21E21E19D19
No Connect (NC)
IO_L18P_GC_25IO_L18N_GC_25IO_L19P_GC_25IO_L19N_GC_25IO_L0P_26IO_L0N_26IO_L1P_26IO_L1N_26IO_L2P_26IO_L2N_26IO_L3P_26IO_L3N_26IO_L4P_26IO_L4N_VREF_26IO_L5P_26IO_L5N_26IO_L6P_26IO_L6N_26IO_L7P_26IO_L7N_26IO_L8P_SRCC_26IO_L8N_SRCC_26IO_L9P_MRCC_26IO_L9N_MRCC_26IO_L10P_MRCC_26IO_L10N_MRCC_26IO_L11P_SRCC_26IO_L11N_SRCC_26IO_L12P_VRN_26IO_L12N_VRP_26IO_L13P_26IO_L13N_26
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 2:Pinout Tables
Table 2-5:FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T, and SX475T (Cont’d)
Bank2626262626262626262626263232323232323232323232323232323232323232
Pin Description
Pin Number
H22J22A18A19K21K22B18C18L20L21C22D22AG15AF15AK14AJ14AJ15AH15AL15AL14AG16AF16AN15AM15AJ17AJ16AP16AP15AH17AG17AC15AD15
No Connect (NC)
IO_L14P_26IO_L14N_VREF_26IO_L15P_26IO_L15N_26IO_L16P_26IO_L16N_26IO_L17P_26IO_L17N_26IO_L18P_26IO_L18N_26IO_L19P_26IO_L19N_26IO_L0P_32IO_L0N_32IO_L1P_32IO_L1N_32IO_L2P_32IO_L2N_32IO_L3P_32IO_L3N_32IO_L4P_32IO_L4N_VREF_32IO_L5P_32IO_L5N_32IO_L6P_32IO_L6N_32IO_L7P_32IO_L7N_32IO_L8P_SRCC_32IO_L8N_SRCC_32IO_L9P_MRCC_32IO_L9N_MRCC_32
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FPGA可编程逻辑器件芯片XC6VLX760-1FFG1760C中文规格书 - 图文
