Spartan-3 FPGA Family: Pinout Descriptions
PQ208: 208-lead Plastic Quad Flat Pack
The 208-lead plastic quad flat package, PQ208, supports three different Spartan-3 devices, including the XC3S50, the XC3S200, and the XC3S400. The footprints for the XC3S200 and XC3S400 are identical, as shown in Table 93 and Figure 47. The XC3S50, however, has fewer I/O pins resulting in 17 unconnected pins on the PQ208 package, labeled as “N.C.” In Table 93 and Figure 47, these unconnected pins are indicated with a black diamond symbol (?).
All the package pins appear in Table 93 and are sorted by bank number, then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier.
If there is a difference between the XC3S50 pinout and the pinout for the XC3S200 and XC3S400, then that difference is highlighted in Table 93. If the table entry is shaded grey, then there is an unconnected pin on the XC3S50 that maps to a user-I/O pin on the XC3S200 and XC3S400. If the table entry is shaded tan, then the unconnected pin on the XC3S50 maps to a VREF-type pin on the XC3S200 and XC3S400. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C. pin on the XC3S50 to the same VREF voltage. This provides maximum flexibility as you could potentially migrate a design from the XC3S50 device to an XC3S200 or XC3S400 FPGA without changing the printed circuit board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx
Pinout Table
Table 93:PQ208 Package Pinout
Bank00000000000000000011111
IOION.C. (?)IO/VREF_0IO_L01N_0/VRP_0IO_L01P_0/VRN_0IO_L25N_0IO_L25P_0IO_L27N_0IO_L27P_0IO_L30N_0IO_L30P_0IO_L31N_0IO_L31P_0/VREF_0IO_L32N_0/GCLK7IO_L32P_0/GCLK6VCCO_0VCCO_0IOIOIO
IO_L01N_1/VRP_1IO_L01P_1/VRN_1
XC3S50 Pin NameXC3S200, XC3S400
Pin NamesIOIO
IO/VREF_0IO/VREF_0IO_L01N_0/VRP_0IO_L01P_0/VRN_0IO_L25N_0IO_L25P_0IO_L27N_0IO_L27P_0IO_L30N_0IO_L30P_0IO_L31N_0IO_L31P_0/VREF_0IO_L32N_0/GCLK7IO_L32P_0/GCLK6VCCO_0VCCO_0IOIOIO
IO_L01N_1/VRP_1IO_L01P_1/VRN_1
PQ208 Pin NumberP189P197P200P205P204P203P199P198P196P194P191P190P187P185P184P183P188P201P167P175P182P162P161
TypeI/OI/OVREFVREFDCIDCII/OI/OI/OI/OI/OI/OI/OVREFGCLKGCLKVCCOVCCOI/OI/OI/ODCIDCI
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
FG320 Footprint
X-Ref Target - Figure 50Bank 01ABGNDI/OL16P_7VREF_7Bank 17I/OL30N_02I/OL01N_0VRP_03I/OL01P_0VRN_04I/OL15N_05I/OL15P_06GND8I/OL30P_09I/OL31P_0VREF_010I/OL31N_1VREF_111I/O12I/OVREF_113GND14I/OL16N_115I/OL10N_1VREF_116I/OL01N_1VRP_117I/OL01P_1VRN_118GNDGNDI/OL01P_7VRN_7I/OVREF_0I/OL09N_0I/OL25N_0I/OL25P_0VCCAUXVCCO_0I/OL31N_0I/OL31P_1VCCO_1VCCAUXI/OI/OL16P_1I/OL10P_1TMSI/OL01N_2VRP_2GNDI/OL01P_2VRN_2I/OL16N_2CDI/OL16N_7I/OL01N_7VRP_7I/OL09P_0I/OL10N_0VCCO_0I/OL27N_0I/OL28N_0GNDGNDI/OL30N_1I/OL28N_1VCCO_1I/OL15N_1I/OL15P_1I/OL16P_2I/OL17N_7I/OL17P_7I/OL19P_7TDII/OL10P_0I/OVREF_0I/OL27P_0I/OL28P_0I/OI/OL32N_0GCLK7I/OI/OL32N_1GCLK5I/OL30P_1I/OL28P_1I/OL24P_1I/OL24N_1TDOI/OL19N_2I/OL17N_2I/OL17P_2VREF_2Bank 7L20P_7L20N_7L21N_7L29P_1L27P_1L27N_1L21P_2L19P_2L20N_2L20P_2FGNDI/OL23P_7VCCO_7I/OL21P_7I/OL22P_7VCCINTVCCINTI/OL29P_0I/OL32P_0GCLK6I/OL32P_1GCLK4VCCO_1I/OL29N_1VCCINTVCCINTI/OL22N_2I/OL21N_2VCCO_2I/OL23P_2GNDI/OGHI/OL23N_7VCCAUXI/OL24P_7I/OL24N_7I/OL22N_7VCCINTGNDVCCO_0VCCO_0VCCO_1GNDVCCINTI/OL22P_2I/OL24N_2I/OL24P_2VCCAUXL23N_2VREF_2I/OL35N_7I/OL35P_7I/OL34P_7I/OL34N_7I/OL27N_7I/OL27P_7VREF_7VCCO_7GNDGNDGNDGNDVCCO_2I/OL27N_2I/OL27P_2I/OL34P_2I/OL34N_2VREF_2I/OL35N_2I/OL35P_2JKI/OL39N_7I/OL39P_7GNDI/OL40P_7I/OL40N_7VREF_7I/OVCCO_7GNDI/OGNDVCCO_2I/OL40P_2VREF_2I/OL40N_2GNDI/OL39P_2I/OL39N_2I/OL40N_6I/OL40P_6VREF_6GNDI/OL34N_6VREF_6I/OL39P_6I/OL39N_6I/OVCCO_6GNDGNDVCCO_3I/OL39N_3I/OL39P_3I/OGNDI/OL34P_3VREF_3I/OL40N_3VREF_3I/OL40P_3LMI/OL35P_6I/OL35N_6I/OL34P_6I/OL27P_6I/OL27N_6VCCO_6GNDGNDGNDGNDVCCO_3I/OL27P_3I/OL27N_3I/OL34N_3I/OL35P_3I/OL35N_3I/OL24P_6VCCAUXI/OL23N_6I/OL23P_6I/OL22P_6VCCINTGNDVCCO_5VCCO_5VCCO_4VCCO_4GNDVCCINTI/OL22N_3I/OL23N_3I/OL23P_3VREF_3VCCAUXI/OL24N_3Bank 6L21N_6L22N_6L22P_3L21P_3L24P_3PI/OL20P_6I/OL20N_6I/OL19P_6I/OL21P_6I/OM0L27N_5VREF_5I/OL27P_5I/OI/OL32P_5GCLK2I/OL32P_4GCLK0I/OL30P_4D3I/OI/OL27P_4D1I/OL25P_4I/OL06N_4VREF_4I/OL21N_3I/OL17N_3I/OL20P_3I/OL20N_3RTI/OL17P_6VREF_6I/OL17N_6I/OL19N_6M2I/OL15P_5I/OL15N_5I/OL28N_5D6I/OL30N_5I/OVREF_5I/OVREF_4I/OL29N_4I/OL25N_4I/OL06P_4I/ODONEL17P_3VREF_3I/OL19N_3I/OL19P_3I/OL16P_6I/OL01P_6VRN_6I/OL01N_6VRP_6I/OL06P_5I/OL06N_5I/OVCCO_5L28P_5D7VCCAUXI/OL30P_5GNDI/OGNDI/OL31N_4INIT_BI/OL29P_4I/OL27N_4DIND0VCCAUXVCCO_4I/OL10N_4I/OCCLKL01P_3VRN_3I/OL01N_3VRP_3I/OL16N_3UVI/OL16N_6GNDI/OI/OM1L10P_5VRN_5I/OL16P_5I/OVCCO_5L31N_5D4VCCO_4I/OVREF_4I/OL10P_4I/OL09N_4I/OL01N_4VRP_4GNDI/OL16P_3I/OL01N_5RDWR_BI/OL10N_5VRP_5GNDL01P_5CS_BI/OL16N_5GNDI/OL29P_5VREF_5I/OL29N_5I/OL31P_5D5I/OL31P_4DOUTBUSYI/OL28P_4I/OL28N_4GNDI/OI/OL09P_4I/OL01P_4VRN_4I/OVREF_4GNDBank 5Bank 4ds099-3_16_121103Figure 50:FG320 Package Footprint (Top View)156I/O: Unrestricted, general-purpose user I/O1670
DCI: User I/O or reference resistor input for bank
CONFIG: Dedicated configuration pinsN.C.: No unconnected pins in this package
128440
DUAL: Configuration pin, then possible userI/O
GCLK: User I/O or global clock buffer inputJTAG: Dedicated JTAG port pinsGND: Ground
2928128
VREF: User I/O or input voltage reference for bank
VCCO: Output voltage supply for bankVCCINT: Internal core voltage supply (+1.2V)
VCCAUX: Auxiliary voltage supply (+2.5V)
DS099 (v3.1) June 27, 2013Product Specification
Bank 3NI/OGNDL24N_6VREF_6VCCO_6I/OI/OI/OVCCINTVCCINTI/OL32N_4GCLK1I/OL30N_4D2I/OL32N_5GCLK3VCCINTVCCINTI/OI/OVCCO_3I/OGNDBank 2EI/OI/OI/OL19N_7VREF_7I/OPROG_BHSWAP_ENI/OI/OL29N_0I/OI/OI/OTCKI/OI/OI/OI/OSpartan-3 FPGA Family: Pinout Descriptions
Table 100:FG456 Package Pinout (Cont’d)
Bank5555555555555555566666666666666666666666
3S400 Pin Name
IO_L27N_5/VREF_5IO_L27P_5IO_L28N_5/D6IO_L28P_5/D7IO_L29N_5IO_L29P_5/VREF_5IO_L30N_5IO_L30P_5IO_L31N_5/D4IO_L31P_5/D5IO_L32N_5/GCLK3IO_L32P_5/GCLK2VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5IO
IO_L01N_6/VRP_6IO_L01P_6/VRN_6IO_L16N_6IO_L16P_6IO_L17N_6IO_L17P_6/VREF_6IO_L19N_6IO_L19P_6IO_L20N_6IO_L20P_6IO_L21N_6IO_L21P_6IO_L22N_6IO_L22P_6IO_L23N_6IO_L23P_6
IO_L24N_6/VREF_6IO_L24P_6N.C. (?)N.C. (?)IO_L27N_6IO_L27P_6
3S1000, 3S1500, 3S2000FG456
Pin NamePin NumberIO_L27N_5/VREF_5IO_L27P_5IO_L28N_5/D6IO_L28P_5/D7IO_L29N_5IO_L29P_5/VREF_5IO_L30N_5IO_L30P_5IO_L31N_5/D4IO_L31P_5/D5IO_L32N_5/GCLK3IO_L32P_5/GCLK2VCCO_5VCCO_5VCCO_5VCCO_5VCCO_5IO
IO_L01N_6/VRP_6IO_L01P_6/VRN_6IO_L16N_6IO_L16P_6IO_L17N_6IO_L17P_6/VREF_6IO_L19N_6IO_L19P_6IO_L20N_6IO_L20P_6IO_L21N_6IO_L21P_6IO_L22N_6IO_L22P_6IO_L23N_6IO_L23P_6
IO_L24N_6/VREF_6IO_L24P_6IO_L26N_6IO_L26P_6IO_L27N_6IO_L27P_6
W9V9AB9AA9Y10W10AB10AA10W11V11AA11Y11T9T10T11U8Y8Y1Y3Y2W4W3W2W1V5U5V4V3V2V1T6T5U4T4U3U2T3R4T2T1
TypeVREFI/ODUALDUALI/OVREFI/OI/ODUALDUALGCLKGCLKVCCOVCCOVCCOVCCOVCCOI/ODCIDCII/OI/OI/OVREFI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OVREFI/OI/OI/OI/OI/O
DS099 (v3.1) June 27, 2013
Product Specification
FPGA可编程逻辑器件芯片XC2S200-6FGG456I中文规格书 - 图文
