Packaging Overview
Summary
This chapter covers the following topics:???
Introduction
Device/Package Combinations and Maximum I/OsPin Definitions
Introduction
This section describes the pinouts for Virtex?-5 devices in the 1.00mm pitch flip-chip fine-pitch BGA packages.
Virtex-5 devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for improved signal integrity and jitter. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins.
All of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). Pins that are not available for the smaller devices are listed in the “No Connects” column of each table.
For Virtex-5Q devices, the EF package is offered. The only difference between an EF and an FF package is that the discrete substrate capacitors on the EF package are coated with epoxy. The coating is comprised of an undercoat epoxy that is dispensed under the
capacitors and an overcoat epoxy that is dispensed over the top of the capacitors. All other package construction characteristics of the EF matches that of the FF package. The EF package changes are noted in Chapter4, “Mechanical Drawings.”
Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/O standards (see UG190: Virtex-5 FPGA User Guide). Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table1-7 provides definitions for all pin types.
For information on package electrical characteristics and how the characteristics are measured, refer to UG112: Device Package User Guide found on the Xilinx website.For the latest Virtex-5 FPGA pinout information, check the Xilinx website for any updates to this document.
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Table 2-1:FF323 Package—LX20T and LX30T (Continued)
Bank
Pin Description
Pin Number
No Connect (NC)
131313131313131313131313131313131313131313131313131717171717171717
IO_L7N_SM2N_13IO_L8P_CC_SM1P_13IO_L8N_CC_SM1N_13(2)IO_L9P_CC_SM0P_13IO_L9N_CC_SM0N_13(2)IO_L10P_CC_13IO_L10N_CC_13(2)IO_L11P_CC_13IO_L11N_CC_13(2)IO_L12P_VRN_13IO_L12N_VRP_13IO_L13P_13IO_L13N_13IO_L14P_13IO_L14N_VREF_13IO_L15P_13IO_L15N_13IO_L16P_13IO_L16N_13IO_L17P_13IO_L17N_13IO_L18P_13IO_L18N_13IO_L19P_13IO_L19N_13IO_L4P_17IO_L4N_VREF_17IO_L5P_17IO_L5N_17IO_L6P_17IO_L6N_17IO_L7P_17IO_L7N_17
L17N12M11K16L16N18M18M14L13P18N17L14K14R17P17N13M13R15R16P14P15N16M16N15M15M10N11T17T16T12R12T18U18
Virtex-5 FPGA Packaging and Pinout Specification
FF1760 Package—LX110, LX155, LX220, and LX330
Table 2-10:
Bank272727272727272727272727272727272727272727272727272828282828282828
FF1760 Package—LX110, LX155, LX220, and LX330 (Continued)
Pin Description
Pin Number
A35D35D36C36C35A37A36B37B36C38D38C39C40B39B38A39A40A41B41B42C41D40D41E42D42C13D13B11C11B12A12D11D12
No Connect (NC)
IO_L7N_27 IO_L8P_CC_27 IO_L8N_CC_27(2)IO_L9P_CC_27 IO_L9N_CC_27(2)IO_L10P_CC_27 IO_L10N_CC_27(2)IO_L11P_CC_27 IO_L11N_CC_27(2)IO_L12P_VRN_27 IO_L12N_VRP_27 IO_L13P_27 IO_L13N_27 IO_L14P_27 IO_L14N_VREF_27 IO_L15P_27 IO_L15N_27 IO_L16P_27 IO_L16N_27 IO_L17P_27 IO_L17N_27 IO_L18P_27 IO_L18N_27 IO_L19P_27 IO_L19N_27 IO_L0P_28 IO_L0N_28 IO_L1P_28 IO_L1N_28 IO_L2P_28 IO_L2N_28 IO_L3P_28 IO_L3N_28
LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2024
FF1760 Package—LX110, LX155, LX220, and LX330
Table 2-10:
Bank303030303030303030303030303131313131313131313131313131313131313131
FF1760 Package—LX110, LX155, LX220, and LX330 (Continued)
Pin Description
Pin NumberAW10BB9BA10AY8AY9AW11AW12BA12BB12BB11BA11AY13AY12E14D15E15F14D16D17F16F15F17E17E20F20D18E18E19F19D22D23D21D20
No Connect (NC)
IO_L13N_30 IO_L14P_30 IO_L14N_VREF_30 IO_L15P_30 IO_L15N_30 IO_L16P_30 IO_L16N_30 IO_L17P_30 IO_L17N_30 IO_L18P_30 IO_L18N_30 IO_L19P_30 IO_L19N_30 IO_L0P_31 IO_L0N_31 IO_L1P_31 IO_L1N_31 IO_L2P_31 IO_L2N_31 IO_L3P_31 IO_L3N_31 IO_L4P_31 IO_L4N_VREF_31 IO_L5P_31 IO_L5N_31 IO_L6P_31 IO_L6N_31 IO_L7P_31 IO_L7N_31 IO_L8P_CC_31 IO_L8N_CC_31(2)IO_L9P_CC_31 IO_L9N_CC_31(2)
LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220
Virtex-5 FPGA Packaging and Pinout Specification
FPGA可编程逻辑器件芯片XC6VLX760-1FFG1760I中文规格书 - 图文
