However, there is additional resistance present between the device ball and the input of the receiver buffer, as shown in Figure1. This resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer).
Figure115.Differential Resistance of LVDS Differential Pin Pair (RD)
Package Ball0.3 ?RDPad9.3 ?LVDSInput Buffer0.3 ?9.3 ?Differential On-ChipTermination ResistorPackage BallPadTable52 defines the specification for internal termination resistance for commercial devices.
Table52.Differential On-Chip Termination Symbol
RD (2)
Description
Internal differential termination for LVDS
Conditions
Commercial(1),(3)Industrial(2),(3)
ResistanceMin
110100
Typ Max
135135
165170
Unit
??
Notes to Table52:(1)(2)(3)
Data measured over minimum conditions (Tj = 0 C, VCCIO +5%) and maximum conditions (Tj = 85 C,VCCIO=–5%).
Data measured over minimum conditions (Tj = –40 C, VCCIO +5%) and maximum conditions (Tj = 100 C,VCCIO=–5%).
LVDS data rate is supported for 840 Mbps using internal differential termination.
MultiVolt I/O Interface
The StratixGX architecture supports the MultiVolt I/O interface feature, which allows StratixGX devices in all packages to interface with systems of different supply voltages.
The StratixGX VCCINT pins must always be connected to a 1.5-V power supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V,
High-Speed I/O Specification
Table146.High-Speed I/O Specifications(Part 2 of4)Symbol
fHSDR Device operation(LVDS, LVPECL,
HyperTransport technology)
Notes(1), (2)-6 Speed GradeMin
30030030030010010030030010
Conditions
J = 10J = 8J = 7J = 4J = 2
J = 1 (LVDS and LVPECL only)
-5 Speed GradeMinTyp
30030030030010010030030010
-7 Speed GradeMin
30030030030010010030030010
Max
84084084084062446210001000400
TypMax
840840840840624462840840400
TypMax
840840840840462462840840311
Unit
MbpsMbpsMbpsMbpsMbpsMbpsMbpsMbpsMHz
fHSDRDPA (LVDS, J=10LVPECL)J=8fHSCLK (Clock frequency)(PCML)fHSCLK =fHSDR / WfHSDR Device operation (PCML)
W = 1 to 30
J = 10J = 8J = 7J = 4J = 2J = 1
300300300300100100
4004004004004002506400
300300300300100100
40040040040040025064000.44
300300300300100100
31131131131130020064000.44
MbpsMbpsMbpsMbpsMbpsMbpsUIUIUI
DPA Run LengthDPA Jitter Tolerance(p-p)DPA Minimum Eye opening (p-p)
DPA Receiver Latency
all data rates
0.56
0.44
0.56
0.56
595959
Numberofparallel CLK cycles
StratixGX FPGA Family
Table146.High-Speed I/O Specifications(Part 3 of4)Symbol
DPA Lock Time
Notes(1), (2)-6 Speed GradeMin
Typ
Max
-7 Speed GradeMin
Typ
Max
Unit
Conditions
Stan-dard
Train-ingPat-tern
Trans-itionDen-sity
-5 Speed GradeMinTyp
Max
SPI-4, CSIX
000010
FPGA可编程逻辑器件芯片EP1SGX40DF1020中文规格书 - 图文
