MEMORY存储芯片MT46V128M4P-6T中文规格书

Ball Descriptions

The pin description table below is a comprehensive list of all possible pins for DDR4 de-vices. All pins listed may not be supported on the device defined in this data sheet. Seethe Ball Assignments section to review all pins used on this device.

Table 3: Ball Descriptions

SymbolA[17:0]TypeInputDescriptionAddress inputs: Provide the row address for ACTIVATE commands and the columnaddress for READ/WRITE commands to select one location out of the memory array inthe respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have addi-tional functions, see individual entries in this table.) The address inputs also providethe op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and16Gb parts. A17 connection is part-number specific; Contact vendor for more infor-mation.Auto precharge: A10 is sampled during READ and WRITE commands to determinewhether auto precharge should be performed to the accessed bank after a READ orWRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sam-pled during a PRECHARGE command to determine whether the PRECHARGE appliesto one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged,the bank is selected by the bank group and bank addresses.Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine ifburst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chop-ped). See the Command Truth Table.Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along withCS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated asrow address inputs for the ACTIVATE command. When ACT_n is HIGH (along withCS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as nor-mal commands that use the RAS_n, CAS_n, and WE_n signals. See the CommandTruth Table.Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE,READ, WRITE, or PRECHARGE command is being applied. Also determines whichmode register is to be accessed during a MODE REGISTER SET command.Bank group address inputs: Define the bank group to which an ACTIVATE, READ,WRITE, or PRECHARGE command is being applied. Also determines which mode regis-ter is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in thex4 and x8 configurations. BG1 is not used in the x16 configuration.Stack address inputs: These inputs are used only when devices are stacked; that is,they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins arenot used in the x16 configuration, and are NC on the x4/x8 SDP). DDR4 will support atraditional DDP package, which uses these three signals for control of the second die(CS1_n, CKE1, ODT1). DDR4 is not expected to support a traditional QDP package. Forall other stack configurations, such as a 4H or 8H, it is assumed to be a single-load(master/slave) type of configuration where C0, C1, and C2 are used as chip ID selectsin conjunction with a single CS_n, CKE, and ODT signal.Clock: Differential clock inputs. All address, command, and control input signals aresampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.A10/APInputA12/BC_nInputACT_nInputBA[1:0]InputBG[1:0]InputC0/CKE1,C1/CS1_n,C2/ODT1InputCK_t,CK_cInput