FPGA可编程逻辑器件芯片EP2SGX60CF780C3中文规格书 - 图文

Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsSwitching Characteristics

Table1–35.StratixIII Memory Output Clock Jitter Specification (Note1), (2),(3)

C2

Clock NetworkRegionalRegionalRegionalGlobalGlobalGlobal

VCCL = 1.1V

SymboltJIT(per)tJIT(cc)tJIT(duty)tJIT(per)tJIT(cc)

Min–70–150–80–105–225

Max7015080105225120

C3, I3VCCL = 1.1VMin–85–170–90–128–255–135

Max8517090128255135

C4, I4VCCL = 1.1VMin Max–100–190–100–150–285–150

100190100150285150

C4L, I4L

VCCL = 1.1VMin Max–100–190–100–150–285–150

100190100150285150

VCCL = 0.9VMin Max–120–230–140–180–340–180

120230140180340180

pspspspspspsUnit

ParameterClock period jitterCycle-to-cycle period jitterDuty cycle jitterClock period jitterCycle-to-cycle period jitterDuty cycle jitter

Notes to Table1–35:

tJIT(duty)–120

(1)The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 standard.

(2)The clock jitter specification applies to memory output clock pins generated using differential signal-splitter & DDIO circuits clocked by a PLL output routed on

a regional or global clock network as specified. Use of regional clock networks are recommended whenever possible.(3)The memory output clock jitter stated in the table is applicable when an input jitter of 30ps is applied.

OCT Calibration Block Specifications

Table1–36 shows the on-chip termination calibration block specifications for StratixIII devices.

Table1–36.On-Chip Termination Calibration Block Specification

SymbolOCTUSRCLKtOCTCALtOCTSHIFTtRS_RT

Description

Clock required by OCT calibration blocks Number of OCTUSRCLK clock cycles required for OCT Rs and Rt calibration

Number of OCTUSRCLK clock cycles required for OCT code to shift out per OCT calibration blockTime required to dynamically switch from Rs to Rt

Min————

Typical—1000282.5

Max20———

UnitMHzcyclescyclesns

DCD Specifications

Table1–37 lists the worst case duty cycle distortion for StratixIII devices. Detailed information on duty cycle distortion will be published after characterization. Table1–37.Duty Cycle Distortion on StratixIII I/O Pins(Note1)

Symbol

Output Duty Cycle

Note to Table1–37:

(1)DCD specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated and general

purpose I/O pins.

C2Min45

Max55

Min45

C3Max55

Min45

C4Max55

Unit%

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

I/O Timing

I/O Timing

Timing Model

The DirectDriveTM technology and MultiTrackTM interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all StratixIII device densities and speed grades. This section describes and specifies the performance of I/Os.

All specifications except the fast model are representative of worst-case supply voltage and junction temperature conditions. Fast model specifications are representative of best case process, supply voltage, and junction temperature conditions.

The timing numbers listed in the tables of this section are extracted from the QuartusII software version 8.1.

Preliminary and Final Timing

Timing models can have either preliminary or final status. The QuartusII software issues an informational message during the design compilation if the timing models are preliminary. Table1–38 shows the status of the StratixIII device timing models.Preliminary status means that the timing models are subject to change in future QuartusII releases. Initially, timing numbers are created using simulation results, process data, and other known parameters. Parts of the timing models may be correlated to silicon measurements. Various tests are used to make the preliminary numbers as close to the actual timing parameters as possible.

Final timing models are based on simulation models that are characterized versus the actual device measurements under all allowable operating conditions. When the timing models are final, all or most of the StratixIII family devices have been

completely characterized and no further changes to the timing model are expected.Table1–38.StratixIII Device Timing Model Status

Device

EP3SL50EP3SL70EP3SL110EP3SL150EP3SL200EP3SL340EP3SE50EP3SE80EP3SE110EP3SE260

Preliminary

——————————

Finalvvvvvvvvvv

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

I/O Timing

Table1–40.Default Loading of Different I/O Standards for StratixIII (Part 2 of 2)

I/O Standard

Differential SSTL-18 CLASSII1.8-V Differential HSTL CLASSI1.8-V Differential HSTL CLASSII1.5-V Differential HSTL CLASSI1.5-V Differential HSTL CLASSII1.2-V Differential HSTL CLASSI1.2-V Differential HSTL CLASSIILVDS

Capacitive Load

00000000

UnitpFpFpFpFpFpFpFpF

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing

Table1–58 specifies EP3SL70 row pins input timing parameters for differential I/O standards.

Table1–58.EP3SL70 Row Pins Input Timing Parameters (Part 1 of 2)

ParameterFast ModelIndustrial

Commercial

C2VCCL=1.1V

C3VCCL=1.1V

C4VCCL=1.1V

VCCL=1.1V

C4L

VCCL=0.9V

I3VCCL=1.1V

I4VCCL=1.1V

VCCL=1.1V

I4L

VCCL=0.9V

Units

I/O Standard

Clock

GCLK

LVDS

tsuth

-0.9191.0420.882-0.625-0.9191.0420.882-0.625-0.9191.0420.882-0.625-0.7340.8501.077-0.827-0.7340.8501.077-0.827-0.7430.8591.068-0.818-0.7430.8591.068-0.818-0.7570.8731.054-0.804

-0.9391.0770.896-0.625-0.9391.0770.896-0.625-0.9391.0770.896-0.625-0.7640.8931.081-0.819-0.7640.8931.081-0.819-0.7760.9051.069-0.807-0.7760.9051.069-0.807-0.7880.9171.057-0.795

-0.988-0.952-1.089-1.040-1.316-0.916-1.048-1.000-1.3491.2091.863

1.2052.243

1.3692.446

1.3062.322

1.5802.342

1.1822.291

1.3392.500

1.2802.376

1.6132.393

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

GCLK tsuPLLthGCLK

tsuth

-1.430-1.749-1.896-1.802-1.817-1.783-1.936-1.843-1.865-0.988-0.952-1.089-1.040-1.316-0.916-1.048-1.000-1.3491.2091.863

1.2052.243

1.3692.446

1.3062.322

1.5802.342

1.1822.291

1.3392.500

1.2802.376

1.6132.393

MINI-LVDS

GCLK tsuPLLthGCLK

tsuth

-1.430-1.749-1.896-1.802-1.817-1.783-1.936-1.843-1.865-0.988-0.952-1.089-1.040-1.316-0.916-1.048-1.000-1.3491.2091.863

1.2052.243

1.3692.446

1.3062.322

1.5802.342

1.1822.291

1.3392.500

1.2802.376

1.6132.393

RSDS

GCLK tsuPLLthGCLK

tsuth

-1.430-1.749-1.896-1.802-1.817-1.783-1.936-1.843-1.865-1.085-1.186-1.286-1.234-1.505-1.193-1.291-1.242-1.5431.2741.776

1.3942.019

1.5162.257

1.4512.138

1.7202.163

1.4102.024

1.5312.263

1.4702.144

1.7582.209

DIFFERENTIAL 1.2-V

HSTL CLASS I

GCLK tsuPLLthGCLK

tsuth

-1.375-1.570-1.756-1.667-1.687-1.565-1.751-1.663-1.730-1.085-1.186-1.286-1.234-1.505-1.193-1.291-1.242-1.5431.2741.776

1.3942.019

1.5162.257

1.4512.138

1.7202.163

1.4102.024

1.5312.263

1.4702.144

1.7582.209

DIFFERENTIAL 1.2-V

HSTL CLASSII

GCLK tsuPLLthGCLK

tsuth

-1.375-1.570-1.756-1.667-1.687-1.565-1.751-1.663-1.730-1.094-1.196-1.302-1.250-1.521-1.202-1.307-1.258-1.5591.2831.767

1.4042.009

1.5322.241

1.4672.122

1.7362.147

1.4192.015

1.5472.247

1.4862.128

1.7742.193

DIFFERENTIAL 1.5-V

HSTL CLASS I

GCLK tsuPLLthGCLK

tsuth

-1.366-1.560-1.740-1.651-1.671-1.556-1.735-1.647-1.714-1.094-1.196-1.302-1.250-1.521-1.202-1.307-1.258-1.5591.2831.767

1.4042.009

1.5322.241

1.4672.122

1.7362.147

1.4192.015

1.5472.247

1.4862.128

1.7742.193

DIFFERENTIAL 1.5-V

HSTL CLASSII

GCLK tsuPLLthGCLK

tsuth

-1.366-1.560-1.740-1.651-1.671-1.556-1.735-1.647-1.714-1.107-1.206-1.320-1.268-1.539-1.213-1.324-1.275-1.5761.2951.754

1.4141.999

1.5502.223

1.4852.104

1.7542.129

1.4302.004

1.5642.230

1.5032.111

1.7912.176

DIFFERENTIAL 1.8-V

HSTL CLASS I

GCLK tsuPLLth

-1.354-1.550-1.722-1.633-1.653-1.545-1.718-1.630-1.697

Stratix III Device Handbook, Volume 2

Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics

I/O Timing

Stratix III Device Handbook, Volume 2