Chapter 7:GTX Receiver (RX)
PRBS Detection
Overview
The GTX receiver includes a built-in PRBS checker. This checker can be set to check for one of three industry-standard PRBS patterns. The checker is self-synchronizing and works on the incoming data before comma alignment or decoding. This function can be used to test the signal integrity of the channel.
Ports and Attributes
Table7-25 defines the PRBS detection ports.
Table 7-25:
Port
INTDATAWIDTHPRBSCNTRESET0PRBSCNTRESET1
PRBS Detection Ports
DirInIn
Clock DomainAsyncRXUSRCLK2
Description
Specifies the width of the internal datapath for the entire GTX_DUAL tile.Resets the PRBS error counter.
PRBSCNTRESET is applied synchronously. Receiver test pattern checker control:00: Disable PRBS checkers
In
RXUSRCLK2
01: Enable 27-1 PRBS checker10: Enable 223-1 PRBS checker11: Enable 231-1 PRBS checker
RXPRBSERR goes High when the number of errors in PRBS testing
RXUSRCLK2exceeds the value set by the PRBS_ERR_THRESHOLD attribute.
RXENPRBSTST0[1:0]RXENPRBSTST1[1:0]
RXPRBSERR0RXPRBSERR1
Out
Table7-26 defines the PRBS detection attributes.
Table 7-26:
PRBS Detection Attributes
Type
Description
Sets the error threshold for the PRBS checker. If PRBS testing is enabled, a counter counts the number of errors. If the number of errors exceeds the value of PRBS_ERR_THRESHOLD, the output RXPRBSERR goes High. This attribute is set as a 32-bit hex value.
Attribute
PRBS_ERR_THRESHOLD0PRBS_ERR_THRESHOLD1
32-bit Hex
Description
To use the built-in PRBS checker, RXENPRBSTST is set to match the PRBS pattern being sent to the receiver. The RXENPRBSTST entry in Table7-25 shows the available settings.When the PRBS checker is running, it attempts to find the selected PRBS pattern in the incoming data. When it finds the pattern, it can detect PRBS errors by comparing the incoming pattern with the expected pattern.
The checker counts the number of errors it sees and compares it with
PRBS_ERR_THRESHOLD. When the error count exceeds the threshold, RXPRBSERR is asserted. Asserting PRBSCNTRESET clears RXPRBSERR. GTXRESET, RXCDRRESET, and RXRESET also reset the count.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Configurable Comma Alignment and Detection
Configurable Comma Alignment and Detection
Overview
Serial data must be aligned to symbol boundaries before it can be used as parallel data. To make alignment possible, transmitters send a recognizable sequence, usually called a comma. The receiver searches for the comma in the incoming data. When it finds a comma, it moves the comma to a byte boundary so the received parallel words match the transmitted parallel words.
Figure7-13 shows the alignment to a 10-bit comma. The TX parallel data is on the left. The serial data with the comma is highlighted in the middle. The RX receiving unaligned bits are on the right side.
X-Ref Target - Figure 7-13Stream of Serial Data1001011000010010011010111001100111001011111001011011001010100100010101010101100110All Subsequent DataAligned to CorrectByte BoundaryTransmitted FirstAlignment BlockFinds CommaUG198_c7_12_040507Figure 7-13:Conceptual View of Comma Alignment (Aligning to a 10-Bit Comma)
Figure7-14 shows the TX parallel data is on the left side, and the RX receiving recognizable parallel data is on the right side.
X-Ref Target - Figure 7-14TX Parallel DataData0RX Parallel DataNon-alignedDataCommaCommaTimeData1Data1Data2Data2UG198_c7_13_071807Figure 7-14:Parallel Data View of Comma Alignment
The GTX transceiver includes an alignment block that can be programmed to align specific commas to various byte boundaries, or to manually align data using attribute settings (see Table7-28, page193). SONET A1/A2 alignment is possible using comma double mode. The block can be bypassed to reduce latency if it is not needed.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Configurable Clock Correction
Table7-38 defines the clock correction attributes.
Table 7-38:
Clock Correction AttributesAttribute
Type
Enables clock correction.
TRUE: Clock correction enabled
CLK_CORRECT_USE_0CLK_CORRECT_USE_1
Boolean
FALSE: Clock correction disabled. In this case, set CLK_COR_SEQ_1_1_0/1 = 10'b0100000000, CLK_COR_SEQ_2_0/1 = 10'b0100000000,
CLK_COR_SEQ_1_ENABLE_0/1 = 4'b1111, and CLK_COR_SEQ_2_ENABLE_0/1 = 4'b1111.
This attribute defines the size of the adjustment (number of bytes repeated or skipped) in a clock correction. The bytes skipped or repeated always start from the beginning of the clock correction sequence to allow more bytes to be replaced than in the specified clock correction sequence.
CLK_COR_ADJ_LEN_0CLK_COR_ADJ_LEN_1
1: Not supported(1)
Integer
2: 2-byte adjustment3: Not supported4: 4-byte adjustment
Notes:
1.When CLK_COR_ADJ_LEN_0/1 = 1 and RXDATAWIDTH0/1 = 1(two-byte interface for the RX data), users can use the RocketIO GTXTransceiver Wizard to support this feature.
Description
CLK_COR_DET_LEN_0CLK_COR_DET_LEN_1
Integer
This attribute defines the length of the sequence that the transceiver matches to detect opportunities for clock correction. Valid lengths are from one to four bytes.
Controls whether the RXRUNDISP input status indicates running disparity or inserted-idle (clock correction sequence) flag.
CLK_COR_INSERT_IDLE_FLAG_0CLK_COR_INSERT_IDLE_FLAG_1
Boolean
FALSE: RXRUNDISP indicates running disparity when RXDATA is decoded data.
TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated) clock correction (“Idle”) sequence (when RXDATA is decoded data).
Controls whether the RX elastic buffer must retain at least one clock correction sequence in the byte stream.
CLK_COR_KEEP_IDLE_0CLK_COR_KEEP_IDLE_1
Boolean
FALSE: The transceiver can remove all clock correction sequences to further re-center the RX elastic buffer during clock correction. TRUE: In the final RXDATA stream, the transceiver must leave at least one clock correction sequence per continuous stream of clock correction sequences.
Specifies the maximum RX elastic buffer latency. If the RX elastic buffer exceeds CLK_COR_MAX_LAT, the clock correction circuit replicates incoming clock correction sequences to prevent overflow. Valid values for this attribute range from 3 to 48.
CLK_COR_MAX_LAT_0CLK_COR_MAX_LAT_1
Integer
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S150-6CS144I中文规格书 - 图文
