可编程硬件描述语言VHDL Quartus四选一电路源代码

VHDL Quartus四选一电路源代码

--四选一电路 --------------------- LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ------------------------- ENTITY PROGRAM IS PORT( );

END ENTITY PROGRAM; ------------------------------

ARCHITECTURE BEHAVE OF PROGRAM IS BEGIN

S:IN STD_LOGIC_VECTOR(1 DOWNTO 0); DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DATAOUT:OUT STD_LOGIC

FOURTOONE:

PROCESS(S) BEGIN

IF S=\

DATAOUT<=DATAIN(0);

ELSIF S=\

DATAOUT<=DATAIN(1);

ELSIF S=\

DATAOUT<=DATAIN(2);

ELSIF S=\

DATAOUT<=DATAIN(3);

ELSE

NULL;

END IF;

END PROCESS ;

END ARCHITECTURE BEHAVE;