Chapter 7:Readback and Configuration Verification
X-Ref Target - Figure 7-2CSI_BRDWR_B
WRITEREADWRITED[0:7]CCLK
AA9955662800E000XXXXXXXXXX30UG191_c7_02_110811Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Readback Command Sequences
13.Write the RCRC command, and write one NOOP command.14.Write the DESYNCH command.
15.Write at least 64 bits of NOOP commands to flush the packet buffer. Continue sending
CCLK pulses until DONE goes High.Table7-2 shows the readback command sequence.
Table 7-2:Step
Shutdown Readback Command Sequence (SelectMAP)SelectMAP PortDirection
Configuration Data
FFFFFFFF000000BB
Dummy WordBus Width Sync WordBus Width DetectDummy WordSync Word
Type 1 NOOP Word 0Type 1 Write 1 Word to CMDSHUTDOWN CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDRCRC CommandType 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 Write 1 Word to CMDRCFG CommandType 1 NOOP Word 0Type 1 Write 1 Word to FARFAR Address = 00000000Type 1 Read 0 Words from FDROType 2 Read 147,600 Words from FDROType 1 NOOP Word 0
Type 1 31 more NOOPs Word 0Packet Data Read FDRO Word 0
Explanation
1Write
11220044FFFFFFFFAA995566
23
WriteWrite
20000000300080010000000B2000000030008001
4Write
00000007200000002000000020000000
5Write
20000000200000002000000030008001
6Write
0000000420000000
789
WriteWriteWrite
3000200100000000280060004802409020000000...00000000
1011
ReadWrite
...0000000020000000
Packet Data Read FDRO Word 147599Type 1 NOOP Word 0
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 7:Readback and Configuration Verification
Table 7-2:Step12
Shutdown Readback Command Sequence (SelectMAP) (Continued)SelectMAP PortDirection
Write
Configuration Data
30008001000000052000000030008001
Explanation
Type 1 Write 1 Word to CMDSTART CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDRCRC CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDDESYNCH CommandType 1 NOOP Word 0Type 1 NOOP Word 0
13Write
0000000720000000
1415
WriteWrite
300080010000000D2000000020000000
User logic should strobe readback data while DOUT_BUSY is Low after switching from a write to a read (both CS_B and RDWR_B are Low). DOUT_BUSY must be monitored to determine when the readback data is valid.
When readback is initiated, and after BUSY is deasserted, 42 dummy words are read back. In x16 and x8 modes, the readback cycles multiply by 2 and 4 respectively.Table 7-3:Readback DOUT_BUSY Latency (SelectMAP)
x8
Read to DOUT_BUSY Latency
Notes:
These latencies assume CS_B is deasserted for one cycle when changing from write to read (RDWR_B deassertion). It is best to monitor the BUSY signal for valid readback data.
x163 clocks
x324 clocks
1 clock
Accessing Configuration Registers through the JTAG Interface
JTAG access to the Virtex-5 configuration logic is provided through the JTAG CFG_IN and CFG_OUT registers. The CFG_IN and CFG_OUT registers are not configuration registers, rather they are JTAG registers like BYPASS and BOUNDARY_SCAN. Data shifted into the CFG_IN register go to the configuration packet processor, where they are processed in the same way commands from the SelectMAP interface are processed.
Readback commands are written to the configuration logic by going through the CFG_IN register; configuration memory is read through the CFG_OUT register. The JTAG state transitions for accessing the CFG_IN and CFG_OUT registers are described in Table7-4.
Table 7-4:Step
1234
Shifting in the JTAG CFG_IN and CFG_OUT Instructions
Description
Set and HoldTDI
XXXX
TMS
1010
# of Clocks (TCK)
5122
C lock five1s on TMS to bring the device to the TLR stateMove into the RTI stateMove into the Select-IR stateMove into the Shift-IR State
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Readback Command Sequences
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 7:Readback and Configuration Verification
Table 7-5:Status Register Readback Command Sequence (JTAG)
Set and Hold
Step
Description
Clock five 1s on TMS to bring the device to the TLR state.1
Move into the RTI state.Move into the Select-IR state.Move into the Shift-IR state.
Shift the first nine bits of the CFG_IN instruction, LSB first.2
Shift the MSB of the CFG_IN instruction while exiting SHIFT-IR.
Move into the SELECT-DR state.Move into the SHIFT-DR state.
TDI
XXXX
TMS
10100110
# of Clocks (TCK)
51229122
111000101
(CFG_IN)
1XX
a:0xAA995566b:0x20000000c:0x2800E001d:0x20000000
Shift configuration packets into the CFG_IN data register, MSB first.3
0159
e:0x20000000
Shift the LSB of the last configuration packet while exiting SHIFT-DR.Move into the SELECT-IR state.Move into the SHIFT-IR state.
Shift the first nine bits of the CFG_OUT instruction, LSB first.4
Shift the MSB of the CFG_OUT instruction while exiting Shift-IR.
Move into the SELECT-DR state.Move into the SHIFT-DR state.
Shift the contents of the STAT register out of the CFG_OUT data register.
Shift the last bit of the STAT register out of the CFG_OUT data register while exiting SHIFT-DR.
Move into the Select-IR state.Move into the Shift-IR State.6
Reset the TAP Controller.
0XX
11001100
132912231
111000100
(CFG_OUT)
1XX
0xSSSSSSSS
5
SXXX
1101
1325
The packets shifted in to the JTAG CFG_IN register are identical to the packets shifted in through the SelectMAP interface when reading the STAT register through SelectMAP.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2S150-5FG456C中文规格书 - 图文
