UG-20244 | 2024.04.05
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1.Intel? Agilex? General-Purpose I/O and LVDS SERDESOverview
The Intel? Agilex? I/O system includes a general-purpose I/O (GPIO) interface, aSecure Device Manager (SDM) I/O interface, and a Hard Processor System (HPS) I/Ointerface. Each I/O interface is designed to meet different interfacing requirements.The general-purpose I/O interface system support:???
1.2 V single-ended non-voltage referenced Joint Electron Device EngineeringCouncil (JEDEC) compliant I/O standards.
1.2 V single-ended and differential voltage referenced JEDEC compliant I/Ostandards.
True differential I/O compatible with LVDS and able to interface with LVDS subsetssuch as RSDS, Mini-LVDS, Sub-LVDS, and any I/O standards that use equivalentelectrical specification.
DDR4 memory interface up to 1600 MHz with a Hard Memory Controller (HMC).LVDS serializer/deserializer (SERDES) interface up to 1.6 Gbps.
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The SDM and HPS I/O interfaces can support 1.8 V single-ended non-voltagereferenced I/O standard for SDM and HPS interfacing.Related InformationIntel Agilex Device Data Sheet
1.1. Intel Agilex I/O and Differential I/O Buffers
The I/O bank within the GPIO interface supports differential and single-ended I/Ostandards. The GPIO bank has true differential I/O buffer pairs using the True
Differential Signaling I/O standard, which is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL I/O standards. One true differential buffer pair forms a true
differential channel. When using SERDES, half of the true differential buffers supportdedicated transmitter channels and the other half support dedicated true receiverchannels. When SERDES is not used, you can configure any of the true differentialbuffers to transmitter or receiver channels. Refer to the device pin-out files forlocations of the dedicated receiver and transmitter channels.
Differential voltage referenced output pins are not true differential output pins. Thedifferential voltage referenced I/O standards use two single-ended output pins whereone of the output pins is inverted.
The I/O bank within the HPS and SDM interfaces supports single-ended IO standards.Intel Agilex devices use different power supplies to power I/O buffers for differentinterfaces:
ISO
9001:2015Registered
FPGA可编程逻辑器件芯片EP3C10F256I7中文规格书
