Chapter6
Readback and Configuration Verification
Spartan?-6 devices allow users to read configuration memory through the SelectMAP, ICAP, and JTAG interfaces. During readback, the user reads all configuration memory cells, including the current values on all user memory elements (LUT RAM, SRL16, and block RAM).
To read configuration memory, users must send a sequence of commands to the device to initiate the readback procedure. Once initiated, the device dumps the contents of its
configuration memory to the SelectMAP or JTAG interface. The Accessing Configuration Registers through the SelectMAP Interface section and IEEE Std 1149.1 JTAG describe the steps for reading configuration memory.
Users can send the readback command sequence from a custom microprocessor, CPLD, or FPGA-based system, or use iMPACT to perform JTAG-based readback verify. iMPACT, the device programming software provided with the ISE? software by Xilinx, can perform all readback and comparison functions for Spartan-6 devices and report to the user whether there were any configuration errors.
Once configuration memory is read from the device, the next step is to determine if there are any errors by comparing the readback bitstream to the configuration bitstream. The Verifying Readback Data section explains how this is done.
Preparing a Design for Readback
There are two mandatory bitstream settings for readback using JTAG or SelectMAP: the BitGen security setting must not prohibit readback (-g Security:none), and bitstream encryption must not be used. Additionally, if readback is to be performed through the SelectMAP interface, the port must be set to retain its function after configuration by
setting the persist option in BitGen (-g Persist:Yes), otherwise the SelectMAP data pins revert to user I/O, precluding further configuration operations. Beyond these security and encryption requirements, no special considerations are necessary to enable readback through the boundary-scan port. Also, these requirements are not necessary when using readback via the ICAP. Limitations for readback are:?
Performing a readback while the design is in operation (without providing ashutdown command) results in reading back invalid blockRAM data. The actualcontents of the blockRAM are unaffected.
Performing a readback (with or without a shutdown command) corrupts the contentsof blockRAMs configured in 9K mode.
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Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Readback Command Sequences
Spartan-6 FPGA configuration memory is read from the FDRO (Frame Data Register - Output) configuration register and can be accessed from the JTAG, SelectMAP, and ICAP interfaces. For the JTAG and SelectMAP interfaces, readback is possible while the FPGA design is active or in a shutdown state, although block RAMs cannot be accessed by the user design while they are being accessed by the configuration logic.
Accessing Configuration Registers through the SelectMAP Interface
To read configuration memory through the SelectMAP interface, users must set the
interface for write control to send commands to the FPGA, and then switch the interface to read control to read data from the device. Write and read control for the SelectMAP
interface is determined by the RDWR_B input: the SelectMAP data pins are inputs when the interface is set for Write control (RDWR_B = 0); they are outputs when the interface is set for Read control (RDWR_B = 1).
The CSI_B signal must be deasserted (CSI_B =1) before toggling the RDWR_B signal, otherwise the user causes an abort (refer to SelectMAP ABORT, page157 for details). The procedure for changing the SelectMAP interface from Write to Read Control, or vice versa, is:1.2.
Deassert CSI_B.Toggle RDWR_B.
RDWR_B = 0: Write controlRDWR_B = 1: Read control3.4.5.
X-Ref Target - Figure 6-1Assert CSI_B.
CSI_B is synchronous to CCLK.
This procedure is illustrated in Figure6-1.
CSI_BRDWR_BWRITEREADByte nByte 0Byte nDATA[0:7]Byte 0CCLKUG380_c6_01_042909Figure 6-1:Changing the SelectMAP Port from Write to Read Control
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2V6000-6FF1152I中文规格书
