Feature Descriptions
VITA 57.1 FMC1 HPC Connector (Partially Populated)
[Figure1-2, callout 30]
The VC707 board implements two instances of the FMC HPC VITA 57.1 specification connector. This section discusses the FMC1 HPC J35 connector.
Note:The FMC1 HPC J35 connector is a keyed connector oriented so that a plug-on card faces
away from the VC707 board.
The VITA 57.1 FMC standard calls for two connector densities: a high pin count (HPC) and a low pin count (LPC) implementation. A 400 pin 10x40 position connector form factor is used for both versions. The HPC version is fully populated with all 400 pins present. The LPC version is partially populated with 160 pins.
The 10x40 rows of an FMC HPC connector provides pins for up to:?????
160 single-ended or 80 differential user-defined signals10 GTX transceivers2 GTX clocks4 differential clocks
159 ground and 15 power connections
The VC707 board FMC1 HPC connector J35 implements a subset of the maximum signal and clock connectivity capabilities:???????
80 differential user-defined pairs34 LA pairs (LA00-LA33)24 HA pairs (HA00-HA23)22 HB pairs (HB00-HB21)8 GTX transceivers2 GTX clocks2 differential clocks
The FMC1 HPC signals are distributed across GTX Quads 118 and 119. Each Quad has the VCCO voltage connected to VADJ.
Note:The VC707 board VADJ voltage for the FMC1 HPC (J35) connector is determined by the
FMC VADJ power sequencing logic described in FMC_VADJ Voltage Control.
VITA 57.1 FMC2 HPC Connector (Partially Populated)
[Figure1-2, callout 31]
The VC707 board implements two instances of the FMC HPC VITA 57.1 specification connector. This section discusses the FMC2 HPC J37 connector.
Note:The FMC2 HPC J37 connector is a keyed connector oriented so that a plug-on card faces
away from the VC707 board.
The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A 400pin 10x40 position connector form factor is used for both versions. The HPC version is fully populated with all 400 pins present. The LPC version is partially populated with 160 pins.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
The 10x40 rows of an FMC HPC connector provides pins for up to:?????
160 single-ended or 80 differential user-defined signals10 GTX transceivers2 GTX clocks4 differential clocks
159 ground and 15 power connections
The VC707 board FMC2 HPC connector J37 implements a subset of the maximum signal and clock connectivity capabilities:?
58 differential user-defined pairs (as shipped with the Virtex-7 XC7VX485T-2FFG1761CFPGA installed on the VC707 board, the FMC2 HB00-HB21 bus connections are notsupported. Refer to the Virtex-7FPGA VC707 Evaluation Kit Master Answer Record inAppendixG: References for more information).34 LA pairs (LA00-LA33)24 HA pairs (HA00-HA23)8 GTX transceivers2 GTX clocks2 differential clocks
?????
The FMC2 HPC signals are distributed across GTX Quads 116 and 117. Each Quad has the VCCO voltage connected to VADJ.
Note:The VC707 board VADJ voltage for the FMC2 HPC (J37) connector is determined by the
FMC VADJ power sequencing logic described in FMC_VADJ Voltage Control.
Signaling Speed Ratings:??
Single-ended: 9GHz (18 Gb/s)Differential???
Optimal Vertical: 9GHz (18 Gb/s)Optimal Horizontal: 16GHz (32 Gb/s)High Density Vertical: 7GHz (15 Gb/s)
Mechanical specifications:??
Samtec SEAM/SEAF Series
1.27 mm x 1.27 mm (0.050\
The Samtec connector system is rated for signaling speeds up to 9GHz (18 Gb/s) based on a -3 dB insertion loss point within a two-level signaling environment.
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Feature Descriptions
For external measurements an XADC header (J19) is provided. This header can be used to provide analog inputs to the FPGA's dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0],
VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.
A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure1-35 shows the XADC header connections.
X-Ref Target - Figure 1-35XADC_VNXADC_VAUX0PXADC_VCC5V0VADJXADC_VAUX8NXADC_DXPXADC_VREFXADC_GPIO_1XADC_GPIO_3135791113151719J192468101214161820XADC_VPXADC_VAUX0NXADC_VAUX8PXADC_DXNXADC_VCC_HEADERXADC_GPIO_0XADC_GPIO_2GNDXADC_AGNDXADC_AGNDUG885_c1_32_030512Figure 1-35:XADC Header (J19)
Table1-33 describes the XADC header J19 pin functions.
Table 1-33:
XADC Header J19 Pinout
J19 PinNumber1, 23, 67, 89, 124, 5, 10111314151619, 20, 17, 18
Description
Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as I/O inputs when anti-alias capacitor is not present.
Auxiliary analog input channel 8. Also supports use as I/O inputs when anti-alias capacitor is not present.Access to thermal diode.Analog ground reference.1.25V reference from the board.Filtered 5V supply from board.Analog 1.8V supply for XADC.
VCCO supply for bank which is the source of DIO pins.Digital Ground (board) Reference
Digital I/O. These pins should come from the same bank. These I/Os should not be shared with other functions because they are required to support 3-state operation.
Net NameVN, VPXADC_VAUX0P, NXADC_VAUX8N, P
DXP, DXNXADC_AGNDXADC_VREFXADC_VCC5V0XADC_VCC_HEADER
VADJGND
XADC_GPIO_3, 2, 1, 0
VC707 Evaluation Board
UG885 (v1.8) February 20, 2024
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
Appendix C:Xilinx Constraints File
VC707 Evaluation BoardUG885 (v1.8) February 20, 2024
FPGA可编程逻辑器件芯片XC9536-15VQ44I中文规格书 - 图文
