Chapter 7:GTX Receiver (RX)
FPGA RX Interface
Overview
The FPGA receives RX data from the GTX receiver through the FPGA RX interface. Data is read from the RXDATA port on the positive edge of RXUSRCLK2.
The width of RXDATA can be configured to be one or two bytes wide. The actual width of the port depends on the internal data width of the GTX_DUAL tile, and whether or not the 8B/10B decoder is enabled. Ports widths of 8 bits, 10 bits, 16 bits, 20 bits, 32 bits, and 40 bits are possible.
The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the RX line rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled. RXUSRCLK must be provided for the internal PCS logic in the receiver. This section shows how to drive the parallel clocks and explains the constraints on those clocks for correct operation.
Ports and Attributes
Table7-43 defines the FPGA RX interface ports.
Table 7-43:
Port
FPGA RX Interface Ports
Dir
Clock Domain
Description
Specifies the bit width for the TX and RX paths. The bit width of TX and RX
INTDATAWIDTH InAsync
must be identical for both channels.
0: 16-bit width1: 20-bit width
The REFCLKOUT port from each GTX_DUAL tile provides access to the
reference clock provided to the shared PMA PLL (CLKIN). It can be routed for use in the FPGA logic.
Receive data bus of the receive interface to the FPGA. The width of RXDATA(0/1) depends on the setting of RXDATAWIDTH(0/1).Selects the width of the RXDATA(0/1) receive data connection to the FPGA.
REFCLKOUTRXDATA0[31:0]RXDATA1[31:0]
OutN/A
OutRXUSRCLK2
RXDATAWIDTH0RXDATAWIDTH1
0: One-byte interface => RXDATA(0/1)[7:0]
In
RXUSRCLK2
1: Two-byte interface => RXDATA(0/1)[15:0]2: Four-byte interface => RXDATA(0/1)[31:0]
The clock domain depends on the selected clock (RXRECCLK(0/1), RXUSRCLK(0/1), and RXUSRCLK2(0/1)) for this interface.
Recovered clock from the CDR. Clocks the RX logic between the PMA and the RX elastic buffer. Can be used to drive RXUSRCLK synchronously with incoming data.
When RXPOWERDOWN[1:0] is set to 11, which is P2 the lowest power state, then RXRECCLK of this transceiver is indeterminate. RXRECCLK of this GTX transceiver is either a static 1 or a static 0.
PCS RX system reset. Resets the RX elastic buffer, 8B/10B decoder, comma detect, and other RX registers. This is a per channel subset of GTXRESET.
RXRECCLK0RXRECCLK1
OutN/A
RXRESET0RXRESET1
InAsync
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA RX Interface
Table 7-43:
Port
FPGA RX Interface Ports (Cont’d)
Dir
Clock Domain
Description
This port provides a clock for the internal RX PCS datapath. This clock must always be provided. The rate depends on INTDATAWIDTH where:INTDATAWIDTH is Low; FRXUSRCLK= Line Rate/16INTDATAWIDTH is High; FRXUSRCLK= Line Rate/20
This port synchronizes the FPGA logic with the RX interface. This clock must be positive-edge aligned to RXUSRCLK. The clock rate depends on FRXUSRCLK and RXDATAWIDTH:
RXDATAWIDTH=0; FRXUSRCLK2=2xFRXUSRCLKRXDATAWIDTH=1; FRXUSRCLK2=FRXUSRCLKRXDATAWIDTH=2; FRXUSRCLK2=FRXUSRCLK/2
RXUSRCLK0RXUSRCLK1
InN/A
RXUSRCLK20RXUSRCLK21
InN/A
There are no attributes in this section.
Description
The FPGA RX interface allows parallel received data to be read from the GTX transceiver. For this interface to be used, the following must be done: ??
The width of the RXDATA port must be configured
RXUSRCLK2 and RXUSRCLK must be connected to clocks running at the correct rate.
Configuring the Width of the Interface
Table7-44 shows how to select the interface width for the RX datapath. 8B/10B decoding is discussed in more detail in “Configurable 8B/10B Decoder,” page 200.Table 7-44:
RX Datapath Width Configuration
RXDATAWIDTH(2)
012012012
RXDEC8B10BUSE
N/AN/AN/A000111
FPGARXInterfaceWidth
(bits)
8163210204081632
INTDATAWIDTH(1)
000111111
Notes:
1.The internal datapath is 16 bits when INTDATAWIDTH is Low and 20 bits when INTDATAWIDTH is High.
2.The RXDATA interface is one byte wide when RXDATAWIDTH = 0, two bytes wide whenRXDATAWIDTH = 1, and four bytes when RXDATAWIDTH = 2.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
Figure7-42 shows how RXDATA is received serially when the internal datapath is 16bits (INTDATAWIDTH is Low) and 8B/10B decoding is disabled.
X-Ref Target - Figure 7-42INTDATAWIDTH = 0 and RXDEC8B10BUSE = 0ReceivedLastReceivedFirstReceivedLastReceivedFirstRXDATA151413121110987654321076543210RXDATAWIDTH = 1ReceivedLastRXDATAWIDTH = 0ReceivedFirstRXDATA31302928272625242322212019181716151413121110RXDATAWIDTH = 29876543210UG198_c7_41_010608Figure 7-42:RX Interface with 8B/10B Bypassed (16-Bit Internal Datapath)
Figure7-43 shows how RXDATA is received serially when the internal datapath is 20 bits (INTDATAWIDTH is High) and 8B/10B decoding is disabled. When RXDATA is 10 bits or 20bits wide, the RXDISPERR and RXCHARISK ports are taken from the 8B/10B decoder interface and are used to present the extra bits.
X-Ref Target - Figure 7-43INTDATAWIDTH = 1 and RXDEC8B10BUSE = 0ReceivedLastReceivedFirstReceivedLastReceivedFirstRXDATA151413121110987654321076543210RXDATAWIDTH = 1RXCHARISK[1]RXDISPERR[1]RXCHARISK[0]RXDISPERR[0]RXDATAWIDTH = 0RXCHARISK[0]RXDISPERR[0]ReceivedLastRXDATA3130292827262524232221201918171615141312111098ReceivedFirst76543210RXDATAWIDTH = 2RXCHARISK[3]RXDISPERR[3]RXCHARISK[2]RXDISPERR[2]RXCHARISK[1]RXDISPERR[1]RXCHARISK[0]RXDISPERR[0]UG198_c7_42_010608Figure 7-43:RX Interface with 8B/10B Bypassed (20-Bit Internal Datapath)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA RX Interface
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XC2S150-4FG256I中文规格书 - 图文
