Data Sheet
ADuM1410/ADuM1411/ADuM1412
FEATURES
Low power operation 5 V operation
1.3 mA per channel maximum at 0 Mbps to 2 Mbps 4.0 mA per channel maximum at 10 Mbps 3 V operation
0.8 mA per channel maximum at 0 Mbps to 2 Mbps 1.8 mA per channel maximum at 10 Mbps Bidirectional communication 3 V/5 V level translation
High temperature operation: 105°C Up to 10 Mbps data rate (NRZ)
Programmable default output state
High common-mode transient immunity: >25 kV/μs 16-lead, RoHS compliant, SOIC wide body package Safety and regulatory approvals
UL recognition: 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak
TüV approval: IEC/EN 60950-1
APPLICATIONS
General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM1410/ADuM1411/ADuM14121 are four-channel digital isolators based on Analog Devices, Inc., iCoupler? technology. Combining high speed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with opto-couplers. The usual concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects, are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS VDD1116VDD2GNDADuM14101215GND2VIA3ENCODEDECODE14VOAVIB4ENCODEDECODE13VOBVIC5ENCODEDECODE12VOCVID6ENCODEDECODE11VODDISABLE710CTRL2100-GND189GND028560Figure 1. ADuM1410
VDD11GNDADuM141116VDD21215GND2VIA3ENCODEDECODE14VOAVIB4ENCODEDECODE13VOBVIC5ENCODEDECODE12VOCVOD6DECODEENCODE11VIDCTRL1710CTRL2200-GND189GND028560Figure 2. ADuM1411
VDD1116VDD2GNDADuM14121215GND2VIA3ENCODEDECODE14VOAVIB4ENCODEDECODE13VOBVOC5DECODEENCODE12VICVOD6DECODEENCODE11VIDCTRL1710CTRL2300-GND9GND01828560Figure 3. ADuM1412
devices consume one-tenth to one-sixth the power of optocou-plers at comparable signal data rates.
The ADuM1410/ADuM1411/ADuM1412 isolators provide four independent isolation channels in a variety of channel configu-rations and data rates (see the Ordering Guide) up to 10 Mbps. All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have a default output control pin. This allows the user to define the logic state the outputs are to adopt in the absence of the input power. Unlike other optocoupler alternatives, the ADuM1410/ADuM1411/ ADuM1412 isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.
Data Sheet SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
ADuM1410/ADuM1411/ADuM1412
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective ground. Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1410, Total Supply Current, Four Channels1 DC to 2 Mbps
VDD1 Supply Current VDD2 Supply Current
10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current
ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps
VDD1 Supply Current VDD2 Supply Current
10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current
ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps
VDD1 or VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 or VDD2 Supply Current All Models
Input Currents Logic High Input ThresholdLogic Low Input ThresholdLogic High Output Voltages Logic Low Output Voltages
Symbol IDDI (Q) IDDO (Q)
Min
Typ 0.50 0.38
Max 0.73 0.53
Unit mA mA
Test Conditions/Comments
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
2.4 1.2 8.8 2.8
3.2 1.6 12 4.0
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
2.2 1.8 5.4 3.8
2.8 2.4 7.6 5.3
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q), IDD2
(Q)
2.0 2.6 mA DC to 1 MHz logic signal frequency
IDD1 (10), IDD2 (10) IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE VIH VIL
VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL
?10 2.0
4.6 6.5 mA μA V V V V V V V
5 MHz logic signal frequency 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2, 0 V ≤ VDISABLE ≤ VDD1
+0.01 +10
0.8
(VDD1 or VDD2) ? 0.1 (VDD1 or VDD2) ? 0.4
5.0 4.8 0.0 0.04 0.2
0.1 0.1 0.4
IOx = ?20 μA, VIx = VIxH IOx = ?4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL
Rev. M | Page of 22
ADuM1410/ADuM1411/ADuM1412
Parameter
SWITCHING SPECIFICATIONS
ADuM1410ARWZ/ADuM1411ARWZ/ ADuM1412ARWZ
Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4
Pulse Width Distortion, |tPLH ? tPHL|4 Propagation Delay Skew5
Channel-to-Channel Matching6 ADuM1410BRWZ/ADuM1411BRWZ/ ADuM1412BRWZ
Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4
Pulse Width Distortion, |tPLH ? tPHL|4
Change vs. Temperature Propagation Delay Skew5
Channel-to-Channel Matching, Codirectional Channels6
Channel-to-Channel Matching, Opposing-Directional Channels6 All Models
Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output7
Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate
Input Enable Time8 Input Disable Time8
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
1
Data Sheet
Min
Typ
Max
Unit
Test Conditions/Comments
Symbol
PW tPHL, tPLH PWD tPSK tPSKCD/OD
1 20
65 1000 ns
Mbps
100 ns 40 ns 50 ns 50 ns CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD
10 20
30 5
100 50 5 30 5 6
ns Mbps ns ns ps/°C ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
tR/tF |CMH| |CML| fr tENABLE tDISABLE IDDI (D) IDDO (D)
25 25
2.5 35 35 1.2
2.0 5.0
0.12 0.04
ns kV/μs kV/μs
CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Mbps μs VIA, VIB, VIC, VID = 0 V or VDD1 μs VIA, VIB, VIC, VID = 0 V or VDD1 mA/ Mbps mA/ Mbps
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. M | Page of 22
Data Sheet
ELECTRICAL CHARACTERISTICS—3 V OPERATION
ADuM1410/ADuM1411/ADuM1412
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. All voltages are relative to their respective ground. Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1410, Total Supply Current, Four Channels1 DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current
ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps
VDD1 Supply Current VDD2 Supply Current
10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current
ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps
VDD1 or VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 or VDD2 Supply Current All Models
Input Currents Logic High Input ThresholdLogic Low Input ThresholdLogic High Output Voltages Logic Low Output Voltages
Symbol IDDI (Q) IDDO (Q)
Min
Typ
Max Unit Test Conditions/Comments
0.25 0.38 mA 0.19 0.33 mA
IDD1 (Q) IDD2 (Q)
1.2 0.8
1.6 1.0
mA mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (10) IDD2 (10) 4.5 1.4 6.5 1.8 mA mA
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
1.0 0.9 3.1 2.1
1.9 1.7 4.5 3.0
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q), IDD2 (Q) IDD1 (10), IDD2 (10) IIA, IIB, IIC, IID,
ICTRL1,ICTRL2, IDISABLE VIH VIL
VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL
?10 1.6
1.0 2.6
1.8 3.8
mA mA
DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2, 0 V ≤ VDISABLE ≤ VDD1
+0.01 +10μA
V V V V V V V
0.4
(VDD1 or VDD2) ? 0.1 3.0 (VDD1 or VDD2) ? 0.4 2.8
0.0 0.1 0.04 0.1 0.2 0.4
IOx = ?20 μA, VIx = VIxH IOx = ?4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 400 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL
Rev. M | Page of 22
ADuM1410/ADuM1411/ADuM1412 Data Sheet
MEMORY存储芯片ADM708ARZ-REEL中文规格书 - 图文
