DDR2 SDRAM
MT47H256M4 – 32 Meg x 4 x 8 banksMT47H128M8 – 16 Meg x 8 x 8 banksMT47H64M16 – 8 Meg x 16 x 8 banksFeatures
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VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)Differential data strobe (DQS, DQS#) option4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8DLL to align DQ and DQS transitions with CK8 internal banks for concurrent operationProgrammable CAS latency (CL)Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCKSelectable burst lengths (BL): 4 or 8Adjustable data-output drive strength64ms, 8192-cycle refreshOn-die termination (ODT)
Industrial temperature (IT) optionAutomotive temperature (AT) optionRoHS-compliant
Supports JEDEC clock jitter specification
Options1
?Configuration
–256 Meg x 4 (32 Meg x 4 x 8 banks)–128 Meg x 8 (16 Meg x 8 x 8 banks)–64 Meg x 16 (8 Meg x 16 x 8 banks)?FBGA package (Pb-free) – x16
–84-ball FBGA (8mm x 12.5mm) DieRev :H
–84-ball FBGA (8mm x 12.5mm) DieRev :M
?FBGA package (Pb-free) – x4, x8–60-ball FBGA (8mm x 10mm) DieRev :H
–60-ball FBGA (8mm x 10mm) DieRev :M
?FBGA package (lead solder) – x16
–84-ball FBGA (8mm x 12.5mm) DieRev :H
?FBGA package (lead solder) – x4, x8–60-ball FBGA (8mm x 10mm) DieRev :H
?Timing – cycle time
–1.875ns @ CL = 7 (DDR2-1066)–2.5ns @ CL = 5 (DDR2-800)–2.5ns @ CL = 6 (DDR2-800)–3.0ns @ CL = 5 (DDR2-667)?Self refresh–Standard–Low-power
?Operating temperature
–Commercial (0°C ≤ TC ≤ +85°C)2–Industrial (–40°C ≤ TC ≤ +95°C;–40°C ≤ TA ≤ +85°C)?Revision
Marking
256M4128M864M16HRNFCFSHHWJN-187E-25E-25-3NoneLNoneIT:H / :M
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
Data-OutData-InPDF: 09005aef8565148a1GbDDR2.pdf – Rev. Y 02/14 ENTable 12: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1VAC Characteristics-187E-25E-25-3E-3-37E-5EParameterDQ output accesstime from CK/CK#DQS–DQ skew,DQS to last DQvalid, per group,per accessDQ hold from nextDQS strobeDQ–DQS hold, DQSto first DQ not val-idCK/CK# to DQ, DQSHigh-ZCK/CK# to DQLow-ZData valid outputwindowDQ and DM inputsetup time to DQSDQ and DM inputhold time to DQSDQ and DM inputsetup time to DQSDQ and DM inputhold time to DQSDQ and DM inputpulse widthSymboltACtDQSQMin–350–Max350175Min–400–Max400200Min–400–Max400200Min–450–Max450240Min–450–Max450240Min–500–Max500300Min–600–MaxUnitsNotes600350psps1926, 27tQHStQH–250–300–300–340–340–400–450psps2826, 27,2819, 21,2919, 21,2226, 27MIN = tHP - tQHSMAX = n/aMIN = n/aMAX = tAC (MAX)MIN = 2 × tAC (MIN)MAX = tAC (MAX)MIN = tQH - tDQSQMAX = n/a075200200––––50125250250––––50125250250––––100175300300––––100175300300––––100225350350––––150275400400––––tHZtLZpspsnspspspspstCK2DVWtDSbtDHbtDSatDHatDIPW1Gb: x4, x8, x16 DDR2 SDRAMAC Timing Operating Specifications26, 30,3126, 30,3126, 30,3126, 30,3118, 32MIN = 0.35 × tCKMAX = n/a1Gb: x4, x8, x16 DDR2 SDRAMAC and DC Operating Conditions
AC and DC Operating Conditions
Table 13: Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSSParameterSupply voltageVDDL supply voltageI/O supply voltageI/O reference voltageI/O termination voltage (system)Notes:
1.2.3.4.
SymbolVDDVDDLVDDQVREF(DC)VTTMin1.71.71.70.49 × VDDQVREF(DC) - 40Nom1.81.81.80.50 × VDDQVREF(DC)Max1.91.91.90.51 × VDDQVREF(DC) + 40UnitsVVVVmVNotes1, 22, 32, 345VDD and VDDQ must track each other. VDDQ must be ≤ VDD.VSSQ = VSSL = VSS.
VDDQ tracks with VDD; VDDL tracks with VDD.
VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in theDC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percentof VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.
5.VTT is not applied directly to the device. VTT is a system supply for signal termination re-sistors, is expected to be set equal to VREF, and must track variations in the DC level ofVREF.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
1Gb: x4, x8, x16 DDR2 SDRAMOutput Driver Characteristics
Figure 18: Full Strength Pull-Up Characteristics
0
–20
–40IOUT (mA)–60
–80
–100
–120
0
0.5
1.0VDDQ - VOUT (V)
1.5
Table 22: Full Strength Pull-Up Current (mA)
Voltage (V)0.00.10.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.71.81.9Min0.00–4.30–8.60–12.90–16.90–20.40–23.28–25.44–26.79–27.67–28.38–28.96–29.46–29.90–30.29–30.65–30.98–31.31–31.64–31.96Nom0.00–5.63–11.30–16.52–22.19–27.59–32.39–36.45–40.38–44.01–47.01–49.63–51.71–53.32–54.90–56.03–57.07–58.16–59.27–60.35Max0.00–7.95–15.90–23.85–31.80–39.75–47.70–55.55–62.95–69.55–75.35–80.35–84.55–87.95–90.70–93.00–95.05–97.05–99.05–101.05PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 30: Nominal Slew Rate for tDH
DQS1DQS#1tIStIHtIStIHVDDQVIH(AC)min
VIH(DC)min
DC to VREF regionNominal slew rateVREF(DC)
Nominal slew rateVIL(DC)max
DC to VREF regionVIL(AC)max
VSS
ΔTRHold slew rate VREF(DC) - VIL(DC)max=rising signalΔTRΔTFHold slew rate VIH(DC)min - VREF(DC)=falling signalΔTFNote:1.DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
Figure 31: Tangent Line for tDH
DQS1DQS#1VDDQVIH(AC)min
Nominal lineVIH(DC)min
DC to VREFregiontIStIHtIStIHTangent lineVREF(DC)
Tangent lineVIL(DC)max
Nominal lineDC to VREFregionVIL(AC)max
VSS
Hold slew rate =rising signalTangent line (VREF[DC] - VIL[DC]max)ΔTRΔTFΔTRHold slew rate Tangent line (VIH[DC]min - VREF[DC])=falling signalΔTFNote:1.DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. Y 02/14 EN
MEMORY存储芯片MT29F4G08ABADAH4-ATD中文规格书 - 图文
