Chapter 2: XPHY Architecture
Table 2: Enabling Bidirectional Datapath Control
Control Mechanism
Gating
Related Attributes
?
RX datapath gating: The RX_GATING attribute enablesgating of the RX datapath based on the PHY_RDEN port.While RX_GATING enables gating, the
CONTINUOUS_DQS attribute lets users choose betweenPHY_RDEN operating based in the PLL_CLK or the strobeclock domain.
TX datapath gating: The TX_GATING attribute enablesgating of the TX datapath based on the PHY_WREN port(which is serialized but not inverted when used for
gating) and PHY_WREN operates in the PLL_CLK domain.NIBBESLICE[1] cannot be gated.
?
Tristating
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Tristating: The TBYTE_CTL_# attribute determines
whether tristating is controlled by the T (combinatorial)port or an inverted and serialized PHY_WREN port(which is in the PLL_CLK domain).
T_OUT[5:0] is the tristate control output from the XPHY. Each bit of T_OUT is associated with aNIBBLESLICE, and TBYTE_CTL_# allows each NIBBLESLICE to select its corresponding T_OUTbit to be controlled by either T or PHY_WREN. In other words for a NIBBLESLICE[x], T_OUT[x]reflects the tristate control input selected by TBYTE_CTL_x. If TBYTE_CTL_x = T, T_OUT[x]
(associated with NIBBLESLICE[x]) is controlled via the T[x] input. Because this is a combinatorialroute, T_OUT[x] is not aligned to the data. If TBYTE_CTL_x = PHY_WREN, T_OUT[x] (associatedwith NIBBLESLICE[x]) is controlled through the PHY_WREN port. This input is inverted,serialized, and output synchronously (through T_OUT[x]) with the TX data when used fortristating. For more information, see Controlling Tristate Control.
IMPORTANT! When using 2:1 serialization (TX_DATA_WIDTH = 2), each NIBBLESLICE tristate buffercan only be controlled through the combinatorial T input (TBYTE_CTL_<0-5> = T). Tristate control throughthe PHY_WREN input (TBYTE_CTL_x = PHY_WREN) is only possible for 8:1 and 4:1 serialization(TX_DATA_WIDTH = 8 and 4, respectively).
PHY_RDEN is set up and used to control RX datapath gating is as follows:
?PHY_RDEN controls accepting or rejecting the strobe entering on NIBBLESLICE[0] or frominter-byte or inter-nibble clocking, depending upon the settings of CONTINUOUS_DQS,RX_GATING, and RX_DATA_WIDTH. Always ensure the strobe has stabilized and BISC hascompleted before asserting PHY_RDEN. Refer to Controlling Built-in Self-Calibration for whenBISC is considered completed.?When RX_DATA_WIDTH = don't care, RX_GATING = ENABLE, and CONTINUOUS_DQS =TRUE, then the four bits of PHY_RDEN are OR'd together and that output is used to controlthe gate. If the result of the OR operation is 1, the capture clock is accepted. If it is 0, then thecapture clock is rejected. PHY_RDEN is synchronized to the capture clock for this attributecombination. When CONTINUOUS_DQS = TRUE, send 3 capture clock cycles before sendingdata.
AM010 (v1.2) April 2, 2021
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