Figure15.Receiver PLL & CRU Circuit
Receiver PLL÷ m (1)rx_lockedLow-Speed TX_PLL_CLKInter Transceiver Routing (IQ1)Global Clks, IO Bus, Gen RoutingPFDRX CRUCLKupdownupdownCharge Pump and Loop FilterVCODedicatedLocalREFCLKB÷ 2rx_locktorefclkrx_locktodataRX_INCRUrx_freqlocked[]rx_riv[ ]High-speed RCVD_CLKLow-speed RCVD_CLKNote to Figure15:(1)
m = 8, 10 16, or 20.
The receiver PLLs and CRUs are capable of supporting up to 3.1875Gbps. The input clock frequency for –5 and –6 speed grade devices is limited to 650MHz if designers use the REFCLKB pin or 325MHz if designers use the other clock routing resources. The maximum input clock frequency for –7 speed grade devices is 312.5MHz if designers use the REFCLKB pin or 156.25MHz with the other clock routing resources. An optional
RX_LOCKED port (active low signal) is available to indicate whether the PLL is locked to the reference clock. The receiver PLL has a
programmable loop bandwidth, which can be set to low, medium, or high. The loop bandwidth parameter can be statically set by the QuartusII software.
Transceiver Blocks
Table10 lists the adjustable parameters of the receiver PLL and CRU. All the parameters listed are statically programmable in the QuartusII software.
Table10.Receiver PLL & CRU Adjustable Parameters
Parameter
Input reference frequency rangeData rate supportMultiplication factor (W)PPM detectorBandwidth
Run length detector
Specifications
25MHz to 650MHz500 Mbps to 3.1875 Gbps2, 4, 5, 8, 10, 16, or 20 (1)125, 250, 500, 1,000Low, medium, high
10-bit or 20-bit mode: 5 to 160 in steps of
58-bit or 16-bit mode: 4 to 128 in steps of 4
Note to Table10:(1)
Multiplication factors 2, 4, and 5 can only be achieved with the use of the pre-divider on the REFCLKB port or if the CRU is trained with the low speed clockfrom the transmitter PLL.
The CRU has a built-in switchover circuit to select whether the
voltage-controlled oscillator of the PLL is trained by the reference clock or the data. The optional port rx_freqlocked can be used to monitor when the CRU is in locked to data mode.
In the automatic mode, the following conditions must be met for the CRU to switch from locked to reference to locked to data mode:
■
■
The CRU PLL is within the prescribed PPM frequency thresholdsetting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM) of the CRUreference clock.
The reference clock and CRU PLL output are phase matched (phases are within .08 UI).
The automatic switchover circuit can be overridden by using the optional ports rx_lockedtorefclk and rx_locktodata. Table11 shows the possible combinations of these two signals.
If the rx_lockedtorefclk and rx_locktodata ports are not used, the default is auto mode.
StratixGX FPGA Family
Table11.Possible Combinations of rx_lockedtorefclk & rx_locktodata
rx_locktodata
001
rx_lockedtorefclk
01x
VCO (lock to mode)
AutoReference CLK
DATA
Deserializer (Serial-to-Parallel Converter)
The deserializer converts the serial stream into a parallel 8- or 10-bit data bus. The deserializer receives the least significant bit first. Figure16 is a diagram of the deserializer.Figure16.Deserializer
D9D8D7D6D5D4D3D2D1D0D9D8D7D6D5D4D3D2D1D010High-speedserial clockLow-speedparallel clockWord Aligner
The word aligner aligns the incoming data based on the specific byte boundaries. The word aligner has three customizable modes of operation: bit-slip mode, 16-bit mode, and 10-bit mode, the last of which is available for the basic and SONET modes. The word aligner also has two
non-customizable modes of operation, which are the XAUI and GigE modes.
Transceiver Blocks
StratixGX FPGA Family
Figure18.Word Aligner in 16-Bit Mode
Word AlignerPattern DetectorManualAlignment Mode16-BitMode16-BitModeA1A2ModeA1A1A2A2ModeA1A2ModeA1A1A2A2ModeIn the 16-bit mode, the word aligner and pattern detector automatically aligns and detects a user-defined 16-bit alignment pattern. This pattern can be in the format of A1A2 or A1A1A2A2 (for the SONET protocol). The re-alignment of the byte boundary can be done via a user-controlled port. The 16-bit mode supports only the 8-bit data path in a single-width or double-width mode.
The 16-bit mode is available only for the basic mode and SONET mode. The A1A1A2A2 word alignment pattern option is available only for the SONET mode and cannot be used in the basic mode.Figure19 shows the word aligner in 10-bit mode.
FPGA可编程逻辑器件芯片EP1SGX25CF672I6N中文规格书
