Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII DevicesPassive Serial Configuration
If the Auto-restart configuration after error option is turned on, the devices release their nSTATUS pins after a reset time-out period (maximum of 100μs). After all nSTATUS pins are released and pulled high, the MAXII device can attempt to
reconfigure the chain without needing to pulse nCONFIG low. If this option is turned off, the MAXII device must generate a low-to-high transition (with a low pulse of at least 2μs) on nCONFIG to restart the configuration process.1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin transitions from high to low and back again to high when a configuration error is detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width of 10μs to a maximum pulse width of 500μs, as defined in the tSTATUS specification.In your system, you can have multiple devices that contain the same configuration data. To support this configuration scheme, all device nCE inputs are tied to GND, while nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth device. Devices must be the same density and package. All devices will start and complete configuration at the same time. Figure11–15 shows multi-device PS configuration when both StratixIII devices are receiving the same configuration data.
Figure11–15.Multiple-Device PS Configuration When Both Devices Receive the Same Data
MemoryADDRDATA0VCCPGM (1)VCCPGM (1)10 kΩ10 kΩStratix III DeviceStratix III DeviceCONF_DONEnSTATUSnCEGNDDATA0nCONFIGDCLKMSEL2MSEL1MSEL0nCEOCONF_DONEExternal Host(MAX II Device orMicroprocessor)N.C.(2)VCCPGMGNDnSTATUSnCEnCEON.C.(2)DATA0nCONFIGDCLKMSEL2MSEL1MSEL0VCCPGMGNDGNDNotes to Figure11–15:
(1)Connect the resistor to a supply that provides an acceptable input signal for all StratixIII devices on the chain. VCCPGM must be high enough to
meet the VIH specification of the I/O on the external host. It is recommended to power up all configuration systems’ I/O with VCCPGM.(2)The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple devices.
You can use a single configuration chain to configure StratixIII devices with other Altera devices. To ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, all of the device CONF_DONE and nSTATUS pins must be tied together.
f
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in the Configuration Handbook.
Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII Devices
Passive Serial Configuration
PS Configuration Timing
Figure11–16 shows the timing waveform for PS configuration when using a MAXII device as an external host.
Figure11–16.PS Configuration Timing Waveform (Note1)
tCF2ST1tCFGnCONFIG
tCF2CKnSTATUS(2)
tSTATUStCF2ST0ttCF2CDtST2CK(5)CLKCONF_DONE(3)
tCHtCL(4)tDH(4)DCLKDATA
Bit 0Bit 1Bit 2Bit 3tDSUUser I/O
High-ZBitnUser ModeINIT_DONE
tCD2UMNotes to Figure11–16:
(1)The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(2)Upon power-up, the StratixIII device holds nSTATUS low for the time of the POR delay.(3)Upon power-up, before and during configuration, CONF_DONE is low.
(4)Do not leave DCLK floating after configuration. You should drive it high or low, whichever is more convenient. DATA[0] is available as a user
I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings.
(5)Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
Table11–10 defines the timing parameters for StratixIII devices for PS configuration.
Table11–10.PS Timing Parameters for StratixIII Devices (Part 1 of 2)SymboltCF2CDtCF2ST0tCFGtSTATUStCF2ST1tCF2CKtST2CKtDSUtDHtCHtCLtCLKfMAXtRParameternCONFIG low to CONF_DONE low nCONFIG low to nSTATUS lownCONFIG low pulse width nSTATUS low pulse widthnCONFIG high to nSTATUS highnCONFIG high to first rising edge on DCLKnSTATUS high to first rising edge of DCLKData setup time before rising edge on DCLKData hold time after rising edge on DCLKDCLK high timeDCLK low time DCLK period DCLK frequency Input rise timeMinimum——210—1002504410——Maximum800800—100 (1)100 (1)———————10040Unitsnsns μs μs μs μsμsnsnsnsnsnsMHznsStratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII DevicesPassive Serial Configuration
Figure11–17.PS Configuration Using a Download Cable
VCCPGM (1)VCCPGM (1)10 kΩ(2)10 kΩVCCPGMVCCPGM (1)VCCPGM (1)Stratix III DeviceMSEL2MSEL1MSEL0CONF_DONEnSTATUS10 kΩ10 kΩVCCPGM (1)10 kΩ(2)GNDnCEnCEON.C.Download Cable10-Pin Male Header(PS Mode)Pin 1VCCPGM GNDDCLKDATA0nCONFIGGNDVIO (3)ShieldGND
Notes to Figure11–17:
(1)You should connect the pull-up resistor to the same supply voltage (VCCPGM) as the USB-Blaster, MasterBlaster (VIO pin), ByteBlasterII,
ByteBlasterMV, or EthernetBlaster cable.
(2)You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up resistors on DATA0 and DCLK.
(3)Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device's VCCPGM. Refer to the MasterBlaster
Serial/USB Communications Cable Data Sheet for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable, this pinis a no connect.
You can use a download cable to configure multiple StratixIII devices by connecting each device's nCEO pin to the subsequent device's nCE pin. The first device's nCE pin is connected to GND while its nCEO pin is connected to the nCE of the next device in the chain. The last device's nCE input comes from the previous device, while its nCEO pin is left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the chain. Because all CONF_DONE pins are tied together, all devices in the chain initialize and enter user mode at the same time.
In addition, because the nSTATUS pins are tied together, the entire chain halts configuration if any device detects an error. The Auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the QuartusII software when an error occurs.
Stratix III Device Handbook, Volume 1
Chapter 11:Configuring StratixIII Devices
Passive Serial Configuration
Figure11–18 shows how to configure multiple StratixIII devices with a download cable.
Figure11–18.Multi-Device PS Configuration using a Download Cable
VCCPGM (1)10 kΩVCCPGM (1)VCCPGM10 kΩVCCPGM (1)10 kΩGNDVCCPGM (1)10 kΩVCCPGM (1)10 kΩ(2)Download Cable10-Pin Male Header(PS Mode)Pin 1Stratix III Device 1MSEL2MSEL1MSEL0CONF_DONEnSTATUSDCLKVCCPGM (2)GNDnCEDATA0nCONFIGnCEOGNDVIO(3)GNDVCCPGMStratix III Device 2MSEL2MSEL1MSEL0CONF_DONEnSTATUSDCLKGNDnCEDATA0nCONFIGnCEON.C.Notes to Figure11–18:
(1)Connect the pull-up resistor to the same supply voltage (VCCPGM) as the USB-Blaster, MasterBlaster (VIO pin), ByteBlasterII, ByteBlasterMV, or
EthernetBlaster cable.
(2)You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This is to
ensure that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up resistors on DATA0 and DCLK.
(3)Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device's VCCPGM. Refer to the MasterBlaster
Serial/USB Communications Cable Data Sheet for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable, this pin is a no connect.
f
For more information about how to use the USB-Blaster, MasterBlaster, ByteBlasterII, ByteBlasterMV, or EthernetBlaster cable, refer to the following user guides:
■■■■
USB-Blaster USB Port Download Cable User GuideMasterBlaster Serial/USB Communications Cable User GuideByteBlasterII Parallel Port Download Cable User GuideByteBlasterMV Parallel Port Download Cable User GuideEthernetBlaster Download Cable User Guide
■Stratix III Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S20F780C6N中文规格书 - 图文
