FPGA可编程逻辑器件芯片EP1S20F780C7N中文规格书 - 图文

Figure2–89 shows the block diagram of the Stratix II GX receiver channel.

Figure2–89.Stratix II GX Receiver Channel

Data to R4, R24, C4, ordirect link interconnectUp to 1 Gbps+–DQData RealignmentCircuitry10dataretimed_dataDPADPA_clkSynchronizerDedicatedReceiverInterfaceEight Phase Clocks8diffioclkrefclkFastPLLload_enRegional orglobal clockAn external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. In addition, eight phase-shifted clocks from the VCO can feed to the DPA circuitry.

f

For more information on the fast PLL, see the PLLs in Stratix II GX Devices chapter in volume 2 of the Stratix II GX Handbook.

The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA block selects the closest phase to the center of the serial data eye to sample the incoming data. This allows the source-synchronous circuitry to capture incoming data correctly regardless of the

channel-to-channel or clock-to-channel skew. The DPA block locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used to write the data into the synchronizer.

The synchronizer sits between the DPA block and the data realignment and SERDES circuitry. Since every channel utilizing the DPA block can have a different phase selected to sample the data, the synchronizer is needed to synchronize the data to the high-speed clock domain of the data realignment and the SERDES circuitry.

Stratix II GX Device Handbook, Volume 1

Stratix II GX Architecture

For high-speed source synchronous interfaces such as POS-PHY 4 and the Parallel RapidIO standard, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is

necessary for these protocols because the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. The Stratix II GX device’s high-speed differential I/O circuitry provides dedicated data realignment circuitry for

user-controlled byte boundary shifting. This simplifies designs while saving ALM resources. You can use an ALM-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment.

Fast PLL and Channel Layout

The receiver and transmitter channels are interleaved such that each I/O bank on the left side of the device has one receiver channel and one transmitter channel per LAB row. Figure2–90 shows the fast PLL and channel layout in the EP2SGX30C/D and EP2SGX60C/D devices. Figure2–91 shows the fast PLL and channel layout in EP2SGX60E, EP2SGX90E/F, and EP2SGX130G devices.

Figure2–90.Fast PLL and Channel Layout in the EP2SGX30C/D and EP2SGX60C/D Devices

4LVDSClock42DPAClockQuadrantQuadrantNote(1)

FastPLL 12FastPLL 2QuadrantQuadrant4LVDSClockDPAClockNote to Figure2–90:(1)

See Table2–38 for the number of channels each device supports.

Stratix II GX Device Handbook, Volume 1

Stratix II GX Architecture

Stratix II GX Device Handbook, Volume 1

IEEE Std. 1149.1 JTAG Boundary-Scan Support

Table3–1.StratixII GX JTAG InstructionsJTAG Instruction

SAMPLE/PRELOAD

Instruction Code

00 0000 0101

Description

Allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer.

Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins.

Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation.Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.

Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO.

Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins.

Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding the I/O pins to a state defined by the data in the boundary-scan register.

Used when configuring a StratixII GX device via the JTAG port with a USB-Blaster?, MasterBlaster?, ByteBlasterMV?, or

ByteBlaster II download cable, or when using a .jam or .jbc via an embedded processor or JRunner.

EXTEST(1)00 0000 1111

BYPASS11 1111 1111

USERCODE00 0000 0111

IDCODEHIGHZ (1)

00 0000 011000 0000 1011

CLAMP (1)00 0000 1010

ICR instructions

PULSE_NCONFIGCONFIG_IO (2)

00 0000 000100 0000 1101

Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected.

Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, during, or after

configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction holds nSTATUS low to reset the configuration device. nSTATUS is held low until the IOE configuration register is loaded and the TAP controller state machine transitions to the UPDATE_DR state.

Monitors internal device operation with the SignalTap II embedded logic analyzer.

SignalTap II instructionsNotes to Table3–1:(1)(2)

Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.For more information on using the CONFIG_IO instruction, refer to the MorphIO: An I/O Reconfiguration Solution for Altera Devices White Paper.

Stratix II GX Device Handbook, Volume 1

Configuration & Testing

The Stratix II GX device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables3–2 and 3–3 show the boundary-scan register length and device IDCODE information for Stratix II GX devices.

Table3–2.Stratix II GX Boundary-Scan Register Length

Device

EP2SGX30EP2SGX60EP2SGX90EP2SGX130

Boundary-Scan Register Length

1,3201,5062,0162,454

Table3–3.32-Bit Stratix II GX Device IDCODE

IDCODE (32 Bits)

Device

EP2SGX30EP2SGX60EP2SGX90EP2SGX130

Version (4 Bits)

0000000000000000

Part Number (16 Bits)

0010 0000 1110 00010010 0000 1110 00100010 0000 1110 00110010 0000 1110 0100

Manufacturer Identity

(11 Bits)

000 0110 1110000 0110 1110000 0110 1110000 0110 1110

LSB (1 Bit)

1111

SignalTap II Embedded Logic Analyzer

Stratix II GX devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is

particularly important for advanced packages, such as FineLine BGA packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured.The logic, circuitry, and interconnects in the Stratix II GX architecture are configured with CMOS SRAM elements. Altera? FPGAs are reconfigurable and every device is tested with a high coverage

production test program so you do not have to perform fault testing and can instead focus on simulation and design verification.

Stratix II GX devices are configured at system power-up with data stored in an Altera configuration device or provided by an external controller (for example, a MAX? II device or microprocessor). You can configure Stratix II GX devices using the fast passive parallel (FPP), active serial

Configuration

Stratix II GX Device Handbook, Volume 1