Figure 62: PROGRAM/ERASE Issued to Locked Block
tLBSYR/B#I/OxPROGRAM or ERASEAddress/data inputLocked blockCONFIRM70hREAD STATUS60hBLOCK LOCK READ STATUS (7Ah)
The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protectionstatus of individual blocks. The address cycles have the same format, as shown below,and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins outputthe block lock status register, which contains the information on the protection statusof the block.
Table 20: Block Lock Status Register Bit Definitions
Block Lock Status Register DefinitionsBlock is locked tightBlock is lockedBlock is unlocked, and device is locked tightBlock is unlocked, and device is not locked tightI/O[7:3]XXXXI/O2 (Lock#)0011I/O1 (LT#)0101I/O0 (LT)1010Figure 63: BLOCK LOCK READ STATUS
CLECE#WE#tWHRALERE#I/Ox7AhBLOCK LOCKREAD STATUS
Add 1Add 2Add 3StatusBlock address
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash MemoryOne-Time Programmable (OTP) Operations
Figure 66: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Opera-tion Mode)
CLECE#
tWCtADLtADLWE#
tWBtPROGALE
RE#I/Ox
80hColadd1OTPColadd2page100h00hDINnDINColCol85hadd1add2n+1Serial inputRANDOM DATAColumn addressINPUT commandDINnDIN10hn+1Serial inputPROGRAMcommand70hREAD STATUScommandStatusSERIAL DATAINPUT commandR/B#
Don‘t CareOTP DATA PROTECT (80h-10)
The OTP DATA PROTECT (80h-10h) command is used to prevent further programmingof the pages in the OTP area. To protect the OTP area, the target must be in OTP opera-tion mode.
To protect all data in the OTP area, issue the 80h command. Issue n address cycles in-cluding the column address, OTP protect page address and block address; the columnand block addresses are fixed to 0. Next, write 00h data for the first byte location andissue the 10h command. R/B# goes LOW for the duration of the array programmingtime, tPROG.
After the data is protected, it cannot be programmed further. When the OTP area is pro-tected, the pages within the area are no longer programmable and cannot be unprotec-ted.
The READ STATUS (70h) command is the only valid command for reading status in OTPoperation mode. The RDY bit of the status register will reflect the state of R/B#. Use ofthe READ STATUS ENHANCED (78h) command is prohibited.
When the target is ready, read the FAIL bit of the status register to determine if the oper-ation passed or failed.
If the OTP DATA PROTECT (80h-10h) command is issued after the OTP area has alreadybeen protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
Two-Plane Operations
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each
plane contains a cache register and a data register independent of the other planes. Theplanes are addressed via the low-order block address bits. Specific details are providedin Device and Array Organization.
Two-plane operations make better use of the NAND Flash arrays on these physicalplanes by performing concurrent READ, PROGRAM, or ERASE operations on multipleplanes, significantly improving system performance. Two-plane operations must be ofthe same type across the planes; for example, it is not possible to perform a PROGRAMoperation on one plane with an ERASE operation on another.
When issuing two-plane program or erase operations, use the READ STATUS (70h)command and check whether the previous operation(s) failed. If the READ STATUS(70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use theREAD STATUS ENHANCED (78h) command to determine which plane operation failed.
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
Figure 70: TWO-PLANE PAGE READ
CLE
WE#
ALE
RE#
Page address MPage address MRowadd 3I/Ox00hColadd 1Coladd 2Rowadd 1Rowadd 200hColadd 1Coladd 2Rowadd 1Rowadd 2Rowadd 330htRColumn address JR/B#
Plane 0 addressColumn address JPlane 1 address1CLEWE#ALERE#I/OxDOUT 0DOUT 1DOUTPlane 0 data06hColadd 1Coladd 2Rowadd 1Rowadd 2Rowadd 3E0hDOUT 0DOUT 1DOUTPlane 1 dataPlane 1 addressR/B#1Notes:
1.Column and page addresses must be the same.
2.The least significant block address bit, BA6, must be different for the first- and second-plane addresses.
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
Figure 71: TWO-PLANE PAGE READ with RANDOM DATA READ
tRR/B#RE#I/Ox00hAddress (5 cycles)00hPlane 0 addressAddress (5 cycles)30hPlane 1 addressData outputPlane 0 data05hAddress(2 cycles)E0hData outputPlane 0 data1
R/B#RE#I/Ox06hAddress (5 cycles)E0hPlane 1 addressData outputPlane 1 data05hAddress(2 cycles)E0hData outputPlane 1 data1
Figure 72: TWO-PLANE PROGRAM PAGE
tDBSYtPROGR/B#I/Ox80hAddress (5 cycles)Data input11h1st-plane address
80hAddress (5 cycles)2nd-plane address
Data input10h70hStatusPDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
MEMORY存储芯片N25Q128A11EF840F中文规格书 - 图文
