FPGA可编程逻辑器件芯片EP1S20F672C7N中文规格书 - 图文

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Configuration Schemes

You can load the configuration data for a Stratix II GX device with one of five configuration schemes (refer to Table3–4), chosen on the basis of the target application. You can use a configuration device, intelligent controller, or the JTAG port to configure a Stratix II GX device. A

configuration device can automatically configure a Stratix II GX device at system power-up.

Multiple Stratix II GX devices can be configured in any of the five

configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Stratix II GX FPGAs offer the following:

■■■

Configuration data decompression to reduce configuration filestorage

Design security using configuration data encryption to protectdesigns

Remote system upgrades for remotely updating Stratix II GX designs

Table3–4 summarizes which configuration features can be used in each configuration scheme.

Refer to the Configuring Stratix II & Stratix II GX Devices chapter in

volume 2 of the StratixIIGX Device Handbook for more information about configuration schemes in Stratix II GX devices.

Table3–4.StratixII GX Configuration Features(Part 1 of2)Configuration Scheme

FPPAS

Configuration Method

MAX II device or microprocessor and flash device

Enhanced configuration deviceSerial configuration device

MAX II device or microprocessor and flash device

Design SecurityDecompression

v (1)

v (1)v (2)

vvvv

Remote System Upgrade

vvv (3)vvv

Enhanced configuration deviceDownload cable (4)

PPA

MAX II device or microprocessor and flash device

Stratix II GX Device Handbook, Volume 1

Configuration & Testing

Stratix II GX Device Handbook, Volume 1

Temperature Sensing Diode (TSD)

considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL.

See the PLLs in Stratix II & StratixIIGX Devices chapter in volume 2 of the Stratix II GX Device Handbook for more information on Stratix II GX PLLs.

Stratix II GX devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an external digital thermometer device. These devices steer bias current through the Stratix II GX diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus 1 sign bit). The external device’s output represents the junction temperature of the Stratix II GX device and can be used for intelligent power management.

The diode requires two pins (tempdiodep and tempdioden) on the Stratix II GX device to connect to the external temperature-sensing device, as shown in Figure3–1. The temperature sensing diode is a

passive element and therefore can be used before the Stratix II GX device is powered.

Figure3–1.External Temperature-Sensing Diode

Stratix II GX DeviceTemperature-Sensing DeviceTemperature Sensing Diode (TSD)

tempdiodeptempdiodenStratix II GX Device Handbook, Volume 1

DC and Switching Characteristics

Table4–3.StratixIIGX Device Recommended Operating Conditions(Part 2 of2)Symbol

Note(1)Maximum

85100

Parameter

Operating junction temperature

Conditions

For commercial useFor industrial use

Minimum

0–40

Unit

Notes to Table4–3:(1)(2)

Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.

During transitions, the inputs may overshoot to the voltage shown in Table4–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100mA and periods shorter than 20ns.

Maximum VCC rise time is 100ms, and VCC must rise monotonically from ground to VCC.

VCCPD must ramp-up from 0 V to 3.3 V within 100 μs to 100ms. If VCCPD is not ramped up within this specifiedtime, the StratixIIGX device will not configure successfully. If the system does not allow for a VCCPD ramp-up time of 100ms or less, hold nCONFIG low until all power supplies are reliable.

All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT, VCCPD, and VCCIOare powered.

VCCIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses.

(3)(4)

(5)(6)

Transceiver Block Characteristics

Tables4–4 through 4–6 contain transceiver block specifications.

Table4–4.StratixIIGX Transceiver Block Absolute Maximum Ratings

Symbol

VCCAVCCPVCCRVCCTVCCT_BVCCLVCCH_B

Note to Table4–4:(1)

The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated.

Note(1)

MinimumMaximum

–0.5–0.5–0.5–0.5–0.5–0.5–0.5

4.61.81.81.81.81.82.4

Parameter

Transceiver block supply voltage

Transceiver block supply Voltage

Transceiver block supply voltage

Conditions

Commercial and industrialCommercial and industrialCommercial and industrialCommercial and industrialCommercial and industrialCommercial and industrialCommercial and industrial

Units

VVVVVVV

Stratix II GX Device Handbook, Volume 1

Operating Conditions

Table4–5.StratixIIGX Transceiver Block Operating ConditionsSymbol

VCCAVCCPVCCRVCCTVCCT_BVCCLVCCH_B (2)RREF (1)

Parameter

Transceiver block supply voltage

Reference resistor

Conditions

Commercial and industrialCommercial and industrialCommercial and industrialCommercial and industrialCommercial and industrialCommercial and industrialCommercial and industrialCommercial and industrial

Minimum

3.1351.151.151.151.151.151.151.4252000 –1%

Typical

3.31.21.21.21.21.21.21.52000

Maximum

3.4651.251.251.251.251.251.251.5752000 +1%

Units

VVVVVVVVΩ

Notes to Table4–5:(1)(2)

The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.Refer to the Stratix II GX Device Handbook, volume 2, for more information.

Table4–6.Stratix II GX Transceiver Block AC Specification(Part 1 of6)

-3 Speed Commercial

Speed GradeMin

Reference clockInput

frequency from REFCLK inputInput

frequency from PLD inputInput clock jitter

Absolute VMAX for a REFCLK pin (12)

-622.08

50 -622.08

MHz

Symbol /

Description