SelectMAP Configuration Interface
BitGen. By default, the SelectMAPx8 interface (D0–D7) is preserved unless another SelectMAP width has been selected with the CONFIG_MODE constraint.
Reconfiguration begins when the synchronization word is clocked into the SelectMAP port. The remainder of the operation is identical to configuration as described above.
SelectMAP Data Ordering
In many cases, SelectMAP configuration is driven by a user application residing on a microprocessor, CPLD, or in some cases another FPGA. In these applications, it is
important to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA.
In SelectMAP x8 mode, configuration data is loaded at one byte per CCLK, with the MSB of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from many other devices. For x16 and x32 modes, see “Parallel Bus Bit Order.” This convention can be a source of confusion when designing custom configuration solutions. Table2-6 shows how to load the hexadecimal value 0xABCD into the SelectMAP data bus. Table 2-6:Bit Ordering for SelectMAP 8-Bit ModeCCLK Cycle
12
Notes:
1.D[0:7] represent the SelectMAP DATA pins.
Hex Equivalent
0xAB0xCD
D011
D101
D210
D300
D411
D501
D610
D711
Some applications can accommodate the non-conventional data ordering without
difficulty. For other applications, it can be more convenient for the source configuration data file to be bit swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate bit-swapped PROM files (see “Configuration Data File Formats”).
Figure2-19 shows the bit ordering for x8, x16, and x32 modes. It also shows the bit ordering for Virtex-4 FPGA x32 mode.
Virtex-5 Modex32x16x8
Pin
3130292827262524232221201918171615141312111024252627282930311617181920212223
88
99
9
8
7000
6111
5222
4333
3444
2555
1666
0777
101112131415101112131415
Virtex-4x32 Mode
31302928272625242322212019181716151413121110
9
8
7
6
5
4
3
2
1
0
Figure 2-19:Bit Ordering
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Byte Peripheral Interface Parallel Flash Mode
Table 2-9:Virtex-5 Device BPI Configuration Interface Pins (Continued)
Type
Dedicated or Dual-Purpose
Description
Pin Name INIT_B
Input or Dedicated Before the Mode pins are sampled, INIT_B is an input that can be held Output, Low to delay configuration. After the Mode pins are sampled, INIT_B Open-Drain is an open-drain, active-Low output indicating whether a CRC error
occurred during configuration:
0 = CRC error 1 = No CRC error
When the SEU detection function is enabled, INIT_B is optionally driven Low when a read back CRC error is detected.
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset
CCLK Output
Dedicated Configuration clock output. CCLK does not directly connect to BPI
Flash but is used internally to generate the address and sample read data. Dual
Active-Low Flash chip select output. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash output enable. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash write enable. This output is actively driven High during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Address output. For I/O bank locations, see Table1-2, page17.
FCS_BOutput
FOE_B Output Dual
FWE_BOutputDual
ADDR[25:0]OutputDual
D[15:0]InputDual
Data input, sampled by the rising edge of the FPGA CCLK. For I/O bank location, see Table1-2, page17.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Table 2-9:Virtex-5 Device BPI Configuration Interface Pins (Continued)
Type Output
Dedicated or Dual-Purpose Dual
Description
Revision Select pins. Not used for typical single bitstream applications. RS[1:0] are 3-stated and pulled up with weak resistors during the initial configuration if the HSWAP pin enables the pull ups. If pull ups are disabled, then a weak external pull up is required (after power-up or assertion of PROGRAM_B). RS[1:0] are actively driven Low to load the fallback bitstream when a configuration error is detected. RS[1:0] can also be controlled by the user through the bitstream or ICAP. See “Fallback MultiBoot,” page153.
Pin Name RS[1:0]
CSO_BOutputDual
Parallel daisy chain active-Low chip select output. Not used in single FPGA applications.
Figure2-23 shows the BPI-Up configuration waveforms.
CCLKINIT_BFCS_BFOE_BFWE_BADDR[25:0]
D[M:0]DONE
UG191_c2_26_011708
0D01D12D23D3nDnFigure 2-23:Virtex-5 Device BPI-Up Configuration Waveforms
Notes related to Figure2-23:??????
CCLK is output in BPI modes. The BPI Flash does not require CCLK, but the Virtex-5FPGA uses the rising edge of CCLK to sample D[max:0] pins.
The Virtex-5 FPGA stops loading the bitstream after the DONE pin goes High.Dual-mode configuration I/O switches to User mode after the GTS_cycle. By default,this is one cycle after DONE goes High.M can be 7 or 15.
FCS_B, FOE_B, and FWE_B should have weak pull-ups after configuration througheither I/O constraints or external pull-up resistors.
The first address 0 for BPI-Up is extended for multiple cycles due to the initial latency.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2S200E-7FG456I中文规格书 - 图文
