SII52006-2.2
Introduction
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DSP Block Overview
Stratix?II and StratixIIGX devices have dedicated digital signal
processing (DSP) blocks optimized for DSP applications requiring high data throughput. These DSP blocks combined with the flexibility of programmable logic devices (PLDs), provide you with the ability to implement various high performance DSP functions easily. Complex systems such as CDMA2000, voice over Internet protocol (VoIP), high-definition television (HDTV) require high performance DSP blocks to process data. These system designs typically use DSP blocks as finite impulse response (FIR) filters, complex FIR filters, fast Fourier transform (FFT) functions, discrete cosine transform (DCT) functions, and correlators.
StratixII and StratixIIGX DSP blocks consist of a combination of dedicated blocks that perform multiplication, addition, subtraction, accumulation, and summation operations. You can configure these blocks to implement arithmetic functions like multipliers, multiply-adders and multiply-accumulators which are necessary for most DSP functions.Along with the DSP blocks, the TriMatrixTM memory structures in
StratixII and StratixIIGX devices also support various soft multiplier implementations. The combination of soft multipliers and dedicated DSP blocks increases the number of multipliers available in StratixII and StratixIIGX devices and provides you with a wide variety of
implementation options and flexibility when designing your systems.
See the Stratix II Device Family Data Sheet in volume 1 of the Stratix II Device Handbook or the StratixIIGX Device Family Data Sheet in volume1 of the StratixIIGX Device Handbook for more information on StratixII and StratixIIGX devices, respectively.
Each Stratix II and StratixIIGX device has two to four columns of DSP blocks that efficiently implement multiplication, multiply-accumulate (MAC) and multiply-add functions. Figure6–1 shows the arrangement of one of the DSP block columns with the surrounding LABs. Each DSP block can be configured to support:
■Eight 9 × 9-bit multipliers■Four 18 × 18-bit multipliers■
One 36 × 36-bit multiplier
DSP Blocks in StratixII and StratixIIGX Devices
Figure6–4 shows the multiplier block architecture.
Figure6–4.Multiplier Block Architecture
mult_round (1)mult_saturate (1)signa (1)signb (1)aclr[3..0]shiftinbclock[3..0]shiftinaena[3..0]sourceaData ADENAQQ1.15Round/SaturateData OutDQENACLRNsourcebData BCLRN(3)DENACLRNQ(2)PipelineRegisterOutputRegistermult_is_saturatedDQENACLRNMultiplier BlockDSP BlockshiftoutbshiftoutaNotes to Figure6–4:(1)(2)(3)
These signals are not registered or registered once to match the data path pipeline.You can send these signals through either one or two pipeline registers.
The rounding and/or saturation is only supported in 18 × 18-bit signed multiplication for Q1.15 inputs.
Input Registers
Each multiplier operand can feed an input register or directly to the multiplier. The following DSP block signals control each input register within the DSP block:
■■■
clock[3..0]ena[3..0]aclr[3..0]
The input registers feed the multiplier and drive two dedicated shift output lines, shiftouta and shiftoutb. The dedicated shift outputs from one multiplier block directly feed input registers of the adjacent multiplier below it within the same DSP block or the first multiplier in the next DSP block to form a shift register chain, as shown in Figure6–5. The
Stratix II Device Handbook, Volume 2
DSP Blocks in StratixII and StratixIIGX Devices
Figure6–6.Rounding and Saturation Bits
18 × 18 Multiplication1 SignBit15 Bits2 LSBs1800362 SignBits (1)31 Bits3 LSBs0001 SignBit15 Bits2 LSBs1800Saturated Output Result2 SignBits (1)11131 Bits3 LSBs111000Rounded Output Result2 SignBits (1)31 Bits3 LSBs000+2 SignBits (1)15 Bits18 Bits00000000000000000100000000000000000019 LSBsare Ignored=0000000000000000000Note to Figure6–6:(1)
Both sign bits are the same. The design only uses one sign bit, and the other one is ignored.
If the design performs a multiply_accumulate or multiply_add operation, the multiplier output is input to the
adder/subtractor/accumulator blocks as a 2.31 value, and the three LSBs are 0.
Stratix II Device Handbook, Volume 2
Architecture
Stratix II Device Handbook, Volume 2
Architecture
Stratix II Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S30F780C5中文规格书 - 图文
