赛灵思半导体（深圳）有限公司
Artix-7 FPGA Feature Summary
Table 4:Artix-7 FPGA Feature Summary by Device
Logic Cells
Configurable Logic Blocks
(CLBs)Slices(1)2,0002,6003,6505,2008,15011,80015,85033,650
Max Distributed RAM (Kb)
1712003134006008921,1882,888
Block RAM Blocks(3)
DSP48E1 Slices(2)
18Kb405090100150210270730
36Kb2025455075105135365
Max (Kb)7209001,6201,8002,7003,7804,86013,140
CMTs(4)
7Series FPGAs Data Sheet: Overview
DevicePCIe(5)GTPs
XADC Blocks
Total I/O Banks(6)Max User I/O(7)
XC7A12TXC7A15TXC7A25TXC7A35TXC7A50TXC7A75TXC7A100TXC7A200T
12,80016,64023,36033,28052,16075,520101,440215,360
40458090120180240740
353556610
11111111
244448816
11111111
353556610
150250150250250300300500
Notes: 1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTP transceivers.
Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os
Package(1)Size (mm)Ball Pitch (mm)DeviceXC7A12TXC7A15TXC7A25TXC7A35TXC7A50TXC7A75TXC7A100TXC7A200T
22
1061062
106
2
112
0000
210210210210
GTP
(4)
CPG23610 x 100.5
I/OHR(5)
CPG23810 x 100.5
GTP
(4)
CSG32415 x 150.8
CSG32515 x 150.8
FTG25617 x 171.0
SBG48419 x 190.8
FGG484(2)23 x 231.0
FBG484(2)23 x 231.0
FGG676(3)27 x 271.0
FBG676(3)27 x 271.0
FFG115635 x 351.0
I/OHR(5)
GTP
(4)
I/OHR(5)
GTP
(4)
I/OHR(5)
GTP
(4)
I/OHR(5)
GTP
I/OHR(5)
GTP
(4)
I/OHR(5)
GTP
I/OHR(5)
GTP
(4)
I/OHR(5)
GTP
I/OHR(5)
GTP
I/OHR(5)
2112
0
210
24444
150150150150150
0000
170170170170
4
285
4444
250250285285
4
285
88
300300
8
400
16
500
0
170
4
250
Notes: 1.All packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FGG484 and FBG484 are footprint compatible. 3.Devices in FGG676 and FBG676 are footprint compatible.4.GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.
DS180 (v2.6) February 27, 2018Product Specification
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以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7VX690T-1FFG1158C的详细参数，仅供参考
赛灵思半导体（深圳）有限公司
7Series FPGAs Data Sheet: Overview
Virtex-7 FPGA Feature Summary
Table 8:Virtex-7 FPGA Feature Summary
Device(1)
Logic Cells
Configurable Logic Blocks (CLBs)Slices(2)91,050305,40051,00064,40075,90086,600108,300153,000178,00090,700136,900
Max Distributed RAM (Kb)6,93821,5504,3886,5258,1758,72510,88813,83817,7008,85013,275
Block RAM Blocks(4)
DSP Slices(3)
CMTs
18Kb
36Kb
Max (Kb)
(5)
PCIe
(6)
GTXGTHGTZ
XADC Total I/O BlocksBanks(7)
Max User I/O(8)8501,2007006007006001,0009001,100600300
SLRs(9)
XC7V585TXC7V2000TXC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690TXC7VX980TXC7VX1140TXC7VH580TXC7VH870T
582,7201,954,560326,400412,160485,760554,240693,120979,2001,139,200580,480876,160
1,260 1,5902,160 2,5841,1202,1602,8002,8803,6003,6003,3601,6802,520
1,5001,7602,0602,3602,9403,0003,7601,8802,820
795 28,6201,2927508801,0301,1801,4701,5001,8809401,410
46,51227,00031,68037,08042,48052,92054,00067,68033,84050,760
1824141214202018241218
34224233423
36360056000000
0028480808072964872
000000000816
11111111111
172414121416201822126
N/A4N/AN/AN/AN/AN/AN/A423
Notes: 1.EasyPath?-7 FPGAs are also available to provide a fast, simple, and risk-free solution for cost reducing Virtex-7 T and Virtex-7 XT FPGA designs2.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.3.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.4.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18 Kb blocks.5.Each CMT contains one MMCM and one PLL.6.Virtex-7 T FPGA Interface Blocks for PCI Express support up to x8 Gen 2. Virtex-7 XT and Virtex-7 HT Interface Blocks for PCI Express support up to x8 Gen 3, with the
exception of the XC7VX485T device, which supports x8 Gen 2.7.Does not include configuration Bank 0.8.This number does not include GTX, GTH, or GTZ transceivers.9.Super logic regions (SLRs) are the constituent parts of FPGAs that use SSI technology. Virtex-7 HT devices use SSI technology to connect SLRs with 28.05 Gb/s
transceivers.
DS180 (v2.6) February 27, 2018Product Specification
7Series FPGAs Data Sheet: Overview
Block RAM
Some of the key features of the block RAM include:???
Dual-port 36Kb block RAM with port widths of up to 72Programmable FIFO logic
Built-in optional error correction circuitry
Every 7series FPGA has between 5 and 1,880 dual-port block RAMs, each storing 36Kb. Each block RAM has two completely independent ports that share nothing but the stored data.
Synchronous Operation
Each memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain unchanged.
Programmable Data Width
Each port can be configured as 32K×1, 16K×2, 8K×4, 4K×9 (or8), 2K×18 (or16), 1K×36 (or32), or 512×72 (or64). The two ports can have different aspect ratios without any constraints.
Each block RAM can be divided into two completely independent 18Kb block RAMs that can each be configured to any aspect ratio from 16K×1 to 512×36. Everything described previously for the full 36Kb block RAM also applies to each of the smaller 18Kb block RAMs.
Only in simple dual-port (SDP) mode can data widths of greater than 18bits (18Kb RAM) or 36bits (36Kb RAM) be
accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72.Both sides of the dual-port 36Kb RAM can be of variable width.
Two adjacent 36Kb block RAMs can be configured as one cascaded 64K×1 dual-port RAM without any additional logic.
Error Detection and Correction
Each 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.
FIFO Controller
The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the write and read ports always have identical width.
First word fall-through mode presents the first-written word on the data output even before the first read operation. After the first word has been read, there is no difference between this mode and the standard mode.
DS180 (v2.6) February 27, 2018Product Specification
XC7VX690T-1FFG1158C - 图文
