Chapter 2: XPHY Architecture
2.CNTVALUEOUT of the output delay (RXTX_SEL[x] = 1) of NIBBLESLICE[x] will only be the
delay implemented by DELAY_VALUE_x. The approximate value of a single tap (ps/tap) forthat nibble is then:
Time value of a single tap = DELAY_VALUE_x / Output delay value ofNIBBLESLICE[x]
Another way to find the approximate time value (ps) of a single tap for a given nibble is:1.Set DELAY_VALUE_a to zero and DELAY_VALUE_b to a nonzero value. CNTVALUEOUT of
the input delays (RXTX_SEL[a,b] = 0) will be:
?CNTVALUEOUT[NIBBLESLICE[a]] = align_delay
?CNTVALUEOUT[NIBBLESLICE[b]] = DELAY_VALUE_b + align_delay2.The approximate value of a single tap (ps/tap) for that nibble is then:
Time value of a single tap = (CNTVALUEOUT[NIBBLESLICE[b]] -CNTVALUEOUT[NIBBLESLICE[a]]) / DELAY_VALUE_b
Cascaded delays, implying CASCADE_x = TRUE, render the TX datapath of NIBBLESLICE[x]inoperable. When using cascaded delays, consider the following:
?Xilinx recommends storing half of the total delay in the input delay and the other half in theoutput delay.?The insertion delay between clock and data is not fully compensated for in NIBBLESLICEswith CASCADE_x = TRUE. This typically results in a ~65 ps difference between the clock anddata. To account for this, take ~65 ps/2 and add that value to both the p-quarter and n-quarter delays.
FIFO
This section refers to the FIFO in the RX datapath. The RX datapath FIFO can operate in threemodes:
?FIFO_MODE_x = SYNC: Both read and write sides of the FIFO in NIBBLESLICE[x] share thesame clock.?FIFO_MODE_x = ASYNC: The read and write clocks of the FIFO in NIBBLESLICE[x] share thesame frequency, but can be phase independent.?FIFO_MODE_x = BYPASS: Forwards the data and FIFO write clock in NIBBLESLICE[x] to theprogrammable logic.The following figure is representative of the FIFO operation. The BYPASS mode is not shown.
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
Chapter 2: XPHY Architecture
Figure 9: FIFO in RX Datapath
FIFO_WR_CLKData from DeserializerPL2, 4, or 8XPHYWrite PointerIncrements on FIFO_WR_CLK301234567Qx[7:0]Read PointerIncrements on FIFO_RD_CLK when FIFO_RDEN = 1FIFO_RDEN3SYNCwrptr_sync1wrptr_sync2ASYNC=FIFO_EMPTYFIFO_RD_CLKFIFO_MODE_xDepending on timing, FIFO_EMPTY might also need to be stagedX24054-052720AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-6BG575I中文规格书
