FEATURESMeets EIA RS-485 Standard5 Mbps Data RateSingle 5 V Supply–7 V to +12 V Bus Common-Mode RangeHigh Speed, Low Power BiCMOSThermal Shutdown ProtectionShort-Circuit ProtectionDriver Propagation Delay: 10 nsReceiver Propagation Delay: 15 nsHigh Z Outputs with Power OffSuperior Upgrade for LTC485APPLICATIONSLow Power RS-485 SystemsDTE-DCE InterfacePacket SwitchingLocal Area NetworksData ConcentrationData MultiplexersIntegrated Services Digital Network (ISDN)GENERAL DESCRIPTION
The ADM485 is a differential line transceiver suitable for high speed bidirectional data communication on multipoint bus trans-mission lines. It is designed for balanced data transmission and complies with EIA Standards RS-485 and RS-422. The part contains a differential line driver and a differential line receiver. Both the driver and the receiver may be enabled independently. When disabled, the outputs are three-stated.
The ADM485 operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state if during fault condi-tions a significant temperature increase is detected in the internal driver circuitry.
Up to 32 transceivers may be connected simultaneously on a bus, but only one driver should be enabled at any time. It is important, therefore, that the remaining disabled drivers do not load the bus. To ensure this, the ADM485 driver features high output imped-ance when disabled and when powered down
ADM485FUNCTIONAL BLOCK DIAGRAMADM485RORVCCREBDEADIDGNDThis minimizes the loading effect when the transceiver is not being used. The high impedance driver output is maintained over the entire common-mode voltage range from –7 V to +12 V.The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating).The ADM485 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS with fast switching bipolar technology. All inputs and outputs contain protection against ESD; all driver outputs feature high source and sink current capability. An epitaxial layer is used to guard against latch-up.The ADM485 features extremely fast switching speeds. Minimal driver propagation delays permit transmission at data rates up to5 Mbps while low skew minimizes EMI interference.The part is fully specified over the commercial and industrial temperature range and is available in PDIP, SOIC, and small footprint MSOP packages.
ADM485–SPECIFICATIONSParameterDRIVERDifferential Output Voltage, VODVOD3?|VOD| for Complementary Output StatesCommon-Mode Output Voltage, VOC?|VOD| for Complementary Output StatesOutput Short-Circuit Current (VOUT = High)Output Short-Circuit Current (VOUT = Low)CMOS Input Logic Threshold Low, VINLCMOS Input Logic Threshold High, VINHLogic Input Current (DE, DI)RECEIVERDifferential Input Threshold Voltage, VTHInput Voltage Hysteresis, ?VTHInput ResistanceInput Current (A, B)CMOS Input Logic Threshold Low, VINLCMOS Input Logic Threshold High, VINHLogic Enable Input Current (RE)CMOS Output Voltage Low, VOLCMOS Output Voltage High, VOHShort-Circuit Output CurrentThree-State Output Leakage CurrentPOWER SUPPLY CURRENTICC (Outputs Enabled)ICC (Outputs Disabled)Specifications subject to change without notice.(VCC = 5 V ? 5%. All specifications TMIN to TMAX, unless otherwise noted.)
TypMax5.05.05.05.00.230.22502500.8±1.0UnitVVVVVVVmAmAVVμAVmVk?mAmAVVμAVVmAμAmAmATest Conditions/CommentsR = ∞, Test Circuit 1VCC = 5 V, R = 50 ? (RS-422), Test Circuit 1R = 27 ? (RS-485), Test Circuit 1VTST = –7 V to +12 V, Test Circuit 2R = 27 ? or 50 ?, Test Circuit 1R = 27 ? or 50 ?, Test Circuit 1R = 27 ? or 50 ?–7 V ≤ VO ≤ +12 V–7 V ≤ VO ≤ +12 VMin2.01.51.535352.0–0.27012+0.21–0.80.8–7 V ≤ VCM ≤ +12 VVCM = 0 V–7 V ≤ VCM ≤ +12 VVIN = 12 VVIN = –7 V2.0±10.44.0785±1.01.00.62.21IOUT = +4.0 mAIOUT = –4.0 mAVOUT = GND or VCC0.4 V ≤ VOUT ≤ 2.4 VDigital Inputs = GND or VCCDigital Inputs = GND or VCCTIMING SPECIFICATIONSParameter(VCC = 5 V ? 5%. All specifications TMIN to TMAX, unless otherwise noted.)
Min2Typ1018101000MaxUnit15515252522nsnsnsnsnsnsnsTest Conditions/CommentsRLDIFF = 54 ?, CL1 = CL2 = 100 pF, Test Circuit3RLDIFF = 54 ?, CL1 = CL2 = 100 pF, Test Circuit3RLDIFF = 54 ?, CL1 = CL2 = 100 pF, Test Circuit3RL = 110 ?, CL = 50 pF, Test Circuit4RL = 110 ?, CL = 50 pF, Test Circuit4RL = 110 ?, CL = 50 pF, Test Circuit4*RL = 110 ?, CL = 50 pF, Test Circuit4*DRIVERPropagation Delay Input to Output tPLH, tPHLDriver O/P to O/P, tSKEWDriver Rise/Fall Time, tR, tFDriver Enable to Output ValidDriver Disable TimingMatched Enable Switching|tAZH– tBZL|, |tBZH– tAZL|Matched Disable Switching|tAHZ– tBLZ|, |tBHZ– tALZ|RECEIVERPropagation Delay Input to Output, tPLH, tPHLSkew |tPLH– tPHL|Receiver Enable, tEN1Receiver Disable, tEN2Tx Pulse Width DistortionRx Pulse Width Distortion*Guaranteed by characterization.Specifications subject to change without notice.81555113052020nsnsnsnsnsnsCL = 15 pF, Test Circuit 5CL = 15 pF, Test Circuit 5CL = 15 pF, RL = 1 k?, Test Circuit6CL = 15 pF, RL = 1 k?, Test Circuit6REV. E
ADM485
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C, unless otherwise noted.)Table I.TransmittingVCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 VInputsDriver Input (DI). . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 VControl Inputs (DE, RE). . . . . . . . . . –0.3 V to VCC + 0.3 VReceiver Inputs (A, B). . . . . . . . . . . . . . . . . . –9 V to +14 VOutputsDriver Outputs (A, B). . . . . . . . . . . . . . . . . . –9 V to +14 VReceiver Output. . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 VPower Dissipation 8-Lead MSOP. . . . . . . . . . . . . . . . 900 mWθJA, Thermal Impedance. . . . . . . . . . . . . . . . . . . . 206°C/WPower Dissipation 8-Lead PDIP. . . . . . . . . . . . . . . . . 500 mWθJA, Thermal Impedance. . . . . . . . . . . . . . . . . . . . 130°C/WPower Dissipation 8-Lead SOIC. . . . . . . . . . . . . . . . . 450 mWθJA, Thermal Impedance. . . . . . . . . . . . . . . . . . . . 170°C/WOperating Temperature RangeCommercial (J Version). . . . . . . . . . . . . . . . . . . 0°C to 70°CIndustrial (A Version). . . . . . . . . . . . . . . . . –40°C to +85°CStorage Temperature Range. . . . . . . . . . . . –65°C to +150°CLead Temperature (Soldering, 10 sec). . . . . . . . . . . . . 300°CVapor Phase (60 sec). . . . . . . . . . . . . . . . . . . . . . . . . 215°CInfrared (15 sec). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingsfor extended periods of time may affect device reliability.InputsDE110DI10XOutputsB01ZA10ZTable II.ReceivingRE0001InputsA–B≥+0.2 V≤–0.2 VOutputRO101ZInputs OpenXORDERING GUIDEModelADM485ANADM485ARADM485AR-REELADM485ARZ*ADM485ARZ-REEL*ADM485ARMADM485ARM-REELADM485ARM-REEL7ADM485JNADM485JRADM485JR-REELADM485JR-REEL7ADM485JRZ*ADM485JRZ-REEL*ADM485JRZ-REEL7**Z = Lead Free.Temperature Range–40°C to +85°C–40°C to +85°C–40°C to +85°C–40°C to +85°C–40°C to +85°C–40°C to +85°C–40°C to +85°C–40°C to +85°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°C0°C to 70°CPackage OptionN-8R-8R-8R-8R-8RM-8RM-8RM-8N-8R-8R-8R-8R-8R-8R-8BrandingM41M41M41CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Although theADM485 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommendedto avoid performance degradation or loss of functionality.REV. E
ADM485
PIN CONFIGURATIONRO1RE28VCCADM4857BTOP VIEWDE3(Not to Scale)6ADI45GNDPIN FUNCTION DESCRIPTIONSPin No.Mnemonic12345678ROREDEDIGNDABVCCFunctionReceiver Output. When enabled, if A > B by 200 mV, then RO = High. If A < B by 200 mV, thenRO = Low.Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a highimpedance state.Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places it in ahigh impedance state.Driver Input. When the driver is enabled, aLogic Low on DI forces A low and B high while a Logic Highon DI forces A high and B low.Ground Connection, 0 V.Noninverting Receiver Input A/Driver Output A.Inverting Receiver Input B/Driver Output B.Power Supply, 5 V ± 5%.REV. E
Test CircuitsRVODRVOCTest Circuit 1.Driver Voltage Measurement375?VOD360?VTST375?Test Circuit 2.Driver Voltage MeasurementACL1RLDIFFBCL2Test Circuit 3.Driver Propagation DelaySwitching Characteristics3V1.5V1.5V0VtPLHtPHLB1/2VOVOAtSKEW = ?tPLH – tPHL?VO90% POINT90% POINT0V–V10% POINT10% POINTOtRtFFigure 1.Driver Propagation Delay, Rise/Fall Timing3VDE1.5V1.5Vt0VZLtLZA, B2.3VVOL + 0.5VVOLtZHtHZVOHA, BVOH – 0.5V2.3V0VFigure 2.Driver Enable/Disable TimingREV. E
ADM485
VCCARL0V OR 3VS1S2DEBCLVOUTDE INTest Circuit 4.Driver Enable/DisableAVOUTBRECLTest Circuit 5.Receiver Propagation Delay+1.5VVCCS1RL–1.5VS2RECLVOUTRE INTest Circuit 6.Receiver Enable/DisableA, B0V0VtPLHtPHLVOHRO1.5VtSKEW = ?tPLH – tPHL?1.5VVOLFigure 3.Receiver Propagation Delay3VRE
1.5V1.5V0VtZLtLZR
1.5VO/P LOWVOL + 0.5VVOLtZHtHZO/P HIGHVOHR
1.5VVOH – 0.5V0VFigure 4.Receiver Enable/Disable Timing
MEMORY存储芯片ADM485ANZ中文规格书 - 图文
