Spartan-3 FPGA Family: Functional Description
The product of w and n yields the total block RAM capacity. Equation1 and Equation2 show that as the data bus width increases, the number of address lines along with the number of addressable memory locations decreases. Using the permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown in Table14.
Table 14:Port Aspect Ratios for Port A or B
DI/DO Bus Width(w – p Bits)
12481632
DIP/DOP Bus Width (p Bits)
000124
Total Data Path Width (w Bits)
12491836
ADDR Bus Width
(r Bits)
14131211109
No. of Addressable Block RAM Locations (n)Capacity (Bits)
16,3848,1924,0962,0481,024512
16,38416,38416,38418,43218,43218,432
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure15, Figure16, and Figure17. When the WE and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of Figure15, Figure16, and Figure17 during which WE is Low.
X-Ref Target - Figure 15CLKWEDIADDRDOXXXX11112222XXXXaabbccdd0000MEM(aa)11112222MEM(dd)ENDISABLEDREADWRITEMEM(bb)=1111WRITEMEM(cc)=2222READDS099-2_14_091410Figure 15:Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different attributes:
Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure15 during which WE is High.Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the portion of Figure16 during which WE is High.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 22Phase:0o90180270ooo0o90180270ooo0oInput Signal (40% Duty Cycle)tCLKINOutput Signal - Duty Cycle is Always CorrectedCLK2XCLK2X180(1)CLKDVOutput Signal - Attribute Corrects Duty CycleDUTY_CYCLE_CORRECTION = FALSECLK0CLK90CLK180CLK270DUTY_CYCLE_CORRECTION = TRUECLK0CLK90CLK180CLK270DS099-2_10_051907Figure 22:Characteristics of the DLL Clock Outputs
Digital Frequency Synthesizer (DFS)
The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input and a ratio of two user-determined integers. Because of the wide range of possible output frequencies such a ratio permits, the DFS feature provides still further flexibility than the DLL’s basic synthesis options as described in the preceding section. The DFS component’s two dedicated outputs, CLKFX and CLKFX180, are defined in Table19.
The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always exhibit a 50% duty cycle. This is true even when the CLKIN signal does not. These DFS clock outputs are driven at the same time as the DLL’s seven clock outputs.
The numerator of the ratio is the integer value assigned to the attribute CLKFX_MULTIPLY and the denominator is the integer value assigned to the attribute CLKFX_DIVIDE. These attributes are described in Table18.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Simultaneously Switching Output Guidelines
This section provides guidelines for the maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins, of a given output signal standard, that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with
bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality.
Table49 and Table50 provide the essential SSO guidelines. For each device/package combination, Table49 provides the number of equivalent VCCO/GND pairs. The equivalent number of pairs is based on characterization and will possibly not match the physical number of pairs. For each output signal standard and drive strength, Table50 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The Table50 guidelines are categorized by package style. Multiply the appropriate numbers from Table49 and Table50 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines may result in increased power or ground bounce, degraded signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table49 x Table50
The recommended maximum SSO values assume that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ, TQ, PQ) is lower than for ball grid array packages (FG) due to the larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs.Table 49:Equivalent VCCO/GND Pairs per Bank
DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000Notes:
1.2.3.
The VCCO lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each pair of interconnected banks shares three VCCO/GND pairs. Consequently, the per bank number is 1.5.The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. The information in this table also applies to Pb-free packages.
VQ10011––––––
CP132(1)(2)
1.5–––––––
TQ144(1)
1.51.51.5–––––
PQ208222–––––
FT256–333––––
FG320––333–––
FG456––5555––
FG676–––56666
FG900–––––91010
FG1156(2)
––––––1212
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S150E-6FG456C中文规格书 - 图文
