Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (<1pF) across approximately 4\microstrip trace. Standard termination was used for all testing. The propagation delay of the 4\
characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure11 and Figure12.
X-Ref Target - Figure 11X-Ref Target - Figure 12FPGA Output+CREFRREFVMEAS–ds714_12_012109VREFFigure 12:Differential Test Setup
Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it.
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method:
1.Simulate the output driver of choice into the generalized
test setup, using values from Table59.2.Record the time to VMEAS.
3.Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or capacitance value to represent the load.
I/O StandardAttribute
LVTTL (all)LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12
PCI33_3 (rising edge)PCI33_3 (falling edge)PCI66_3 (rising edge)PCI66_3 (falling edge)PCIX (rising edge)PCIX (falling edgeGTLGTLPHSTL_IHSTL_IIHSTL_III
FPGA OutputRREFVMEAS(voltage level when taking delay measurement)CREF (probe capacitance)DS714_11_012109Figure 11:Single Ended Test Setup
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)LVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V
PCI (Peripheral Component Interface), 33 MHz, 3.3VPCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)GTL Plus
HSTL (High-Speed Transceiver Logic), Class IHSTL, Class IIHSTL, Class III
DS714 (v2.2) January 17, 2011Product Specification
RREF (?)1M1M1M1M1M1M2525252525252525502550
CREF(1)(pF)00000010(2)10(2)10(2)10(2)10(3)10(3)00000
VMEAS(V)1.41.651.250.90.750.60.942.030.942.030.942.030.81.0VREFVREF0.9
VREF(V)00000003.303.33.31.21.50.750.751.5
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 99:Package Skew(1)
Symbol
TPKGSKEW
Description
Package Skew(2)
Device
XQ5VLX30T(3)XQ5VLX85XQ5VLX110XQ5VLX110XQ5VLX110TXQ5VLX155TXQ5VLX220TXQ5VLX330TXQ5VSX50TXQ5VSX95TXQ5VSX240T(3)XQ5VFX70TXQ5VFX70TXQ5VFX100TXQ5VFX100TXQ5VFX130TXQ5VFX200T(3)
PackageFF323EF676EF676EF1153EF1136EF1136EF1738EF1738EF665EF1136FF1738EF665EF1136EF1136EF1738EF1738FF1738
Value127142142173163147156155103176161102153144172181164
Unitspspspspspspspspspspspspspspspspsps
Notes:
1.2.3.
Package trace length information is available for these device/package combinations. This information can be used to deskew the package.These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight timefrom Pad to Ball (7.0pspermm).
The EF package is not available for these devices.
Table 100:Sample Window
SymbolTSAMPTSAMP_BUFIONotes:
1.
This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. Thecharacterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:-CLK0 DCM jitter
-DCM accuracy (phase offset)-DCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. Thecharacterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. Thesemeasurements do not include package or clock tree skew.
Description
Sampling Error at Receiver Pins(1)
Sampling Error at Receiver Pins using BUFIO(2)
DeviceAllAll
Speed Grade-2I500400
-1I550450
-1M550450
Unitspsps
2.
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 101:Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Speed Grade-2I–0.541.72
-1I–0.541.91
-1M–0.541.91
Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIOTPSCS/TPHCS
Setup/Hold of I/O clock
ns
Pin-to-Pin Clock-to-Out Using BUFIOTICKOFCS
Clock-to-Out of I/O clock
4.82
5.40
5.40
ns
Revision History
The following table shows the revision history for this document.
Date05/05/0912/17/09
Version1.02.0
Initial Xilinx release.
Description of Revisions
Changed the document classification from Preliminary Product Specification to Product Specification.Updated XQ5VSX240T, XQ5VFX70T, and XQ5VFX200T to production devices in Table54 and Table55.
Updated package information for XQ5VFX200T and XQ5VSX240T in Table99.
Production release of XQ5VFX70T and XQ5VFX100T in the -1M speed grade. This includes changes to Table54 and Table55. Added a -1M column to any table with speed grades. Also updated the -2I speed grade software in Table55 for the XQ5VLX220T and XQ5VSX95T device.
Added -1(M) column to Table4 including values for XQ5VFX70T and XQ5VFX100T. Revised
maximum VOD in Table8. Updated both minimum and maximum VOCM in Table10. Updated minimum DVPPIN in Table40. In Table46, updated TJ4.25 and added note 5. In Table51, added I-grade and M-grade delineation for gain error, bipolar gain error, and ADCCLK revised AIDD maximum specification. Added note 1 to Table57. In Table71, added the FX70T(M) specification for the global clock tree (BUFG) FMAX. Added the FX70T(M) specification for the FOUTMAX to Table74. Added note5 to Table76. Added note 5 to Table77. Added note 3 to Table81.
Revised production release of the XQ5VFX70T and XQ5VFX100T in the -1M speed grade to software version ISE 12.4 using the v1.71 speed specification (see Table55).
07/23/102.1
01/17/112.2
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS.DS714 (v2.2) January 17, 2011Product Specification
FPGA可编程逻辑器件芯片XC2S30-6FGG256I中文规格书 - 图文
