AIIGX51001-4.4
The Arria? II device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power,
programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express? (PCIe?), Ethernet, and
DDR3 memory are easily implemented in your design with the Quartus?II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The ArriaIIdevice family makes designing for applications requiring transceivers operating at up to 6.375Gbps fast and easy.This chapter contains the following sections:
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“ArriaIIDevice Feature” on page1–1“Arria II Device Architecture” on page1–6
“Reference and Ordering Information” on page1–14
ArriaIIDevice Feature
The ArriaIIdevice features consist of the following highlights:
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40-nm, low-power FPGA engine
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Adaptive logic module (ALM) offers the highest logic efficiency in the industryEight-input fracturable look-up table (LUT)
Memory logic array blocks (MLABs) for efficient implementation of smallFIFOs
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High-performance digital signal processing (DSP) blocks up to 550MHz
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Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precisionmultipliers as well as 18 x 36-bit high-precision multiplier
Hardcoded adders, subtractors, accumulators, and summation functionsFully-integrated design flow with the MATLAB and DSP Builder softwarefrom Altera
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Maximum system bandwidth
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Up to 24 full-duplex clock data recovery (CDR)-based transceivers supportingrates between 600Mbps and 6.375Gbps
Dedicated circuitry to support physical layer functionality for popular serialprotocols, including PCIe Gen1 and PCIeGen2, GbpsEthernet, SerialRapidIO? (SRIO), Common Public Radio Interface (CPRI), OBSAI,
SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI(RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,
SerialLiteII, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter(JESD204), and SFI-5.
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Arria II Device Handbook Volume 1: Device Interfaces and IntegrationJuly 2012
Chapter 1:Overview for the Arria II Device FamilyArria II Device Architecture
1PCIe Gen2 protocol is only available in ArriaIIGZ devices.
The following sections provide an overview of the various features of the ArriaII FPGA.
PCIe Hard IP Block
Support
PCIe Gen1PCIe Gen2
Root Port and endpoint configurationsPayloads
Arria II GX Devices
x1, x4, x8—Yes
128-byte to 256-byte
Arria II GZ Devices
x1, x4, x8x1, x4Yes
128-byte to 2K-byte
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII Devices
Logic Array Blocks
The LAB of the Arria II device has a derivative called memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB. The MLAB supports a maximum of 640bits of simple dual-port SRAM. You can configure each ALM in an MLAB as either a 64 × 1 or 32 × 2 block, resulting in a configuration of 64 × 10 or
32 × 20 simple dual-port SRAM blocks. MLAB and LAB blocks always coexist as pairs in ArriaII devices. MLAB is a superset of the LAB and includes all LAB features. Figure2–2 shows an overview of LAB and MLAB topology.
fFor more information about MLABs, refer to the TriMatrix Memory Blocks in ArriaII
Devices chapter.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII DevicesAdaptive Logic Modules
ALM Interconnects
There are three dedicated paths between ALMs: Register Cascade, Carry-chain, and Shared Arithmetic chain. ArriaII devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift
registers. These ALM-to-ALM connections bypass the local interconnect. Figure2–15 shows the shared arithmetic chain, carry chain, and register chain interconnects.Figure2–15.Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
Local interconnectrouting among ALMsin the LABCarry chain & shared
arithmetic chain
routing to adjacent ALM
ALM 1ALM 2Localinterconnect
Register chainrouting to adjacentALM's register input
ALM 3...Clear and Preset Logic ControlLAB Power Management Techniques
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ALM 10LAB-wide signals control the logic for the register‘s clear signal. The ALM directly supports an asynchronous clear function. You can achieve the register preset through the QuartusII software’s NOT-gate push-back logic option. Each LAB supports up to two clears.
ArriaII devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the QuartusII software enables this pin. This device-wide reset overrides all other control signals.
The following techniques are used to manage static and dynamic power consumption within the LAB:
The QuartusII software forces all adder inputs low when ALM adders are not inuse to save AC power.
Arria II LABs operate in high-performance mode or low-power mode. TheQuartusII software automatically chooses the appropriate mode for the LAB,based on the design, to optimize speed versus leakage trade-offs.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
...Chapter 3:Memory Blocks in Arria II DevicesMemory Features
Figure3–5 shows the address clock enable waveform during write cycle for M9K and M144K blocks.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX190EF29I5N中文规格书 - 图文
