Chapter 1: Overview
Chapter 1
Overview
Introduction to Versal ACAP
Versal? adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, AdaptableEngines, and Intelligent Engines with leading-edge memory and interfacing technologies to
deliver powerful heterogeneous acceleration for any application. Most importantly, Versal ACAPhardware and software are targeted for programming and optimization by data scientists andsoftware and hardware developers. Versal ACAPs are enabled by a host of tools, software,libraries, IP, middleware, and frameworks to enable all industry-standard design flows.
Built on the TSMC 7 nm FinFET process technology, the Versal portfolio is the first platform tocombine software programmability and domain-specific hardware acceleration with the
adaptability necessary to meet today's rapid pace of innovation. The portfolio includes six seriesof devices uniquely architected to deliver scalability and AI inference capabilities for a host ofapplications across different markets—from cloud—to networking—to wireless communications—to edge computing and endpoints.
The Versal architecture combines different engine types with a wealth of connectivity andcommunication capability and a network on chip (NoC) to enable seamless memory-mappedaccess to the full height and width of the device. Intelligent Engines are SIMD VLIW AI Enginesfor adaptive inference and advanced signal processing compute, and DSP Engines for fixed point,floating point, and complex MAC operations. Adaptable Engines are a combination of
programmable logic blocks and memory, architected for high-compute density. Scalar Engines,including Arm? Cortex?-A72 and Cortex-R5F processors, allow for intensive compute tasks.The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines thatdeliver over 100x greater compute performance than current server-class of CPUs. This series isdesigned for a breadth of applications, including cloud for dynamic workloads and network formassive bandwidth, all while delivering advanced safety and security features. AI and datascientists, as well as software and hardware developers, can all take advantage of the high-compute density to accelerate the performance of any application.
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
Revision History
SectionTable 45Revision SummaryUpdated description of CONTINUOUS_DQS,FIFO_MODE_<0-5>, RX_CLK_PHASE_N, RX_CLK_PHASE_P,RX_GATING, and TXRX_LOOPBACK_<0-5>.Clarified that NIBBLESLICE[0] must be used for properoutput delay calibration of each NIBBLESLICE in a nibble.Added paragraph about BLI flip-flops.Added note to explain when input VCCO levels can bemodified.Updated JEDEC standard references to reflect 1.2V and 1.5VLVCMOS standards.Updated description of SIM_DEVICE attributes.Replaced NIBBLESLICE with IOL.Added JEDEC specifications JESD8-7A and JESD8-5A toinclude 2.5V and 1.8V LVCMOS standards.Clarified that IBUFDISABLE is not supported in HD IOB.Removed support for 2 mA from DRIVE attribute.11/24/2020 Version 1.1Reset SequenceXPHY UsageTable 57XP IOB Supported Single-Ended StandardsXP IOB IBUFDISABLESingle Data Rate Flip-FlopsHD IOB Supported Single-Ended StandardsTable 110, Table 111, Table 112, Table 113, Table 118, Table119, Table 120, and Table 121Table 114XP XPHY??Removed bullet about XPHY UNISIM primitive.Updated bullet about QBC and DBC functionality.Bidirectional Datapath and Controlling IBUF_DISABLE andDYN_DCITable 4DelaysAdded new sections.Updated Connection (RX) column for CLK_TO_LOWER,CLK_TO_UPPER.??Removed description of tap value from note.Added sentence that CRSE delay cannot be controlledthrough the PL.Controlling DelaysControlling FIFO ModesTristate ControlControlling Tristate ControlTable 14Controlling IBUF_DISABLE and DYN_DCIRegister Interface UnitUpdated section and added Figure 8.Added note about not registering FIFO_EMPTY as part of theFIFO_RDEN = !FIFO_EMPTY connection.Rewrote section.Rewrote first sentence.Updated second bullet in Controlled By column for VTC.Added PHY SM description and sequence.??Added references to Ports and Attributes sections inmost tables.Updated description of bit [2] in Table 19.Table 19Table 20Table 38Table 41Table 44Table 45Reset SequenceUpdated description of bits [0], [1], and [2].Updated description of bit [13].Added new table.Updated description of bits [9:0].Updated description of PHY_RDEN, PHY_WREN, DYN_DCI,RST, TX_RST, and IBUF_DISABLE.Updated description of CONTINUOUS_DQS, ODT_SRC_<0-5>,RX_GATING, TX_INIT_<0-5>, and TX_INIT_TRI.Updated section, including both figures.AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-5FG676C中文规格书
