Clock Network Sources
In ArriaII GX devices, clock input pins, internal logic, transceiver clocks, and PLL outputs can drive the GCLK and RCLK networks, while in Arria II GZ devices, clock input pins, PLL outputs, and internal logic can drive the GCLK and RCLK networks. Table5–2 through Table5–5 on page5–13 list the connectivity between the dedicated clock pins and the GCLK and RCLK networks.
Dedicated Clock Inputs Pins
CLK pins can either be differential clocks or single-ended clocks. ArriaII GX devices support six differential clock inputs or 12 single-ended clock inputs, while Arria II GZ devices support 16 differential clock inputs or 32 single-ended clock inputs. You can also use the dedicated clock input pins CLK[4..15] (for ArriaIIGX devices) and CLK[15..0] (for ArriaIIGZ devices) for high fan-out control signals such as
asynchronous clears, presets, and clock enables for protocol signals such as TRDY and IRDY for PCI Express? (PCIe?) through GCLK or RCLK networks.
Logic Array Blocks
You can drive up to four signals into each GCLK and RCLK network with logic array block (LAB)-routing to allow internal logic to drive a high fan-out, low-skew signal.
1
You cannot drive ArriaII PLLs by internally generated GCLKs or RCLKs. The input clock to the PLL has to come from dedicated clock input pins or PLL-fed GCLKs and RCLKs only.
PLL Clock Outputs
Table5–2 and Table5–3 list the connection between the dedicated clock input pins and GCLKs.
Table5–2.Clock Input Pin Connectivity to GCLK Networks for Arria II GX DevicesClock Resources
4
GCLK[0..3] (1)GCLK[4..7]GCLK[8..11]GCLK[12..15]Note to Table5–2:
(1)GCLK[0..3] is not driven by any clock pins because there are no dedicated clock pins on the left side of the ArriaII GX device.
CLK (p/n Pins)
5—v——
6—v——
7—v——
8——v—
9——v—
10——v—
11——v—
12———v
13———v
14———v
15———v
—v——
Table5–3.Clock Input Pin Connectivity to the GCLK Networks for ArriaIIGZ Devices(Part 1 of 2)
CLK (p/n Pins)
Clock Resources
0
GCLK[0..3]GCLK[4..7]v—
1v—
2v—
3v—
4—v
5—v
6—v
7—v
8——
9——
10——
11——
12——
13——
14——
15——
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II Devices
Clock Networks in ArriaII Devices
Table5–3.Clock Input Pin Connectivity to the GCLK Networks for ArriaIIGZ Devices(Part 2 of 2)
CLK (p/n Pins)
Clock Resources
0
GCLK[8..11]GCLK[12..15]——
1——
2——
3——
4——
5——
6——
7——
8v—
9v—
10v—
11v—
12—v
13—v
14—v
15—v
Table5–4 and Table5–5 list the connectivity between the dedicated clock input pins and RCLKs in Arria II devices. A given clock input pin can drive two adjacent RCLK networks to create a dual-RCLK network.
Table5–4.Clock Input Pin Connectivity to RCLK Networksfor Arria II GX Devices
CLK (p/n Pins)
Clock Resource
4
RCLK [12, 14, 16, 18, 20, 22]RCLK [13, 15, 17, 19, 21, 23]RCLK [24..35]RCLK [36, 38, 40, 42, 44, 46]RCLK [37, 39, 41, 43, 45, 47]v————
5—v———
6v————
7—v———
8——v——
9——v——
10——v——
11——v——
12———v—
13————
14———v
15————v
v—
Table5–5.Clock Input Pin Connectivity to the RCLK Networks for Arria II GZ Devices(Part 1 of 2)
Clock Resource
0
RCLK [0, 4, 6, 10]RCLK [1, 5, 7, 11]RCLK [2, 8]RCLK [3, 9]RCLK [13, 17, 21, 23, 27, 31]RCLK [12, 16, 20, 22, 26, 30]RCLK [15, 19, 25, 29]RCLK [14, 18, 24, 28]RCLK [35, 41]RCLK [34, 40]RCLK [33, 37, 39, 43]RCLK [32, 36, 38, 42]RCLK [47, 51, 57, 61]RCLK [46, 50, 56, 60]v—————————————
1—v————————————
2——v———————————
3———v——————————
4————v—————————
5—————v————————
6——————v———————
CLK (p/n Pins)
7———————v——————
8————————v—————
9—————————v————
10——————————v———
11———————————v——
12————————————v—
13—————————————v
14——————————————
15——————————————
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II DevicesClock Networks in ArriaII Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II Devices
Clock Networks in ArriaII Devices
Clock Output Connections
PLLs in ArriaII GX devices can drive up to 24 RCLK networks and eight GCLK networks, while PLLs in ArriaIIGZ devices can drive up to 20 RCLK networks and four GCLK networks. The QuartusII software automatically assigns PLL clock outputs to RCLK or GCLK networks.
Table5–8 and Table5–9 list the ArriaII PLL connectivity to GCLK networks. Table5–8.PLL Connectivity to GCLKs for Arria II GX Devices
PLL Number
Clock Network
1
GCLK[0..3] GCLK[4..7]GCLK[8..11]GCLK[12..15]v——v
2——vv
3—vv—
4vv——
5——v—
6——v—
Table5–9.PLL Connectivity to the GCLK Networks for Arria II GZ Devices(Note1)
PLL Number
Clock NetworkGCLK[0..3]GCLK[4..7]GCLK[8..11]GCLK[12..15]Note to Table5–9:
(1)Only PLL counter outputs C0 - C3 can drive the GCLK networks.
L2v———
L3 v———
B1—v——
B2—v——
R2——v—
R3——v—
T1———v
T2———v
Table5–10 and Table5–11 list how the PLL clock outputs connect to RCLK networks. Table5–10.RCLK Outputs from PLLs for Arria II GX Devices
Clock Resource
1
RCLK[0..11]RCLK[12..23]RCLK[24..35]RCLK[36..47]v——v
2——vv
PLL Number3—vv—
4vv——
5——v—
6——v—
Table5–11.RCLK Outputs From the PLL Clock Outputs for Arria II GZ Device(Part 1 of 2)
Clock Resource
L2
RCLK[0..11]RCLK[12..31]v—
L3v—
B1—v
PLL NumberB2—v
R2——
R3——
T1——
T2——
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II DevicesClock Networks in ArriaII Devices
Table5–11.RCLK Outputs From the PLL Clock Outputs for Arria II GZ Device(Part 2 of 2)
PLL Number
Clock Resource
L2
RCLK[32..43]RCLK[44..63]——
L3——
B1——
B2——
R2v—
R3v—
T1—v
T2—v
Clock Control Block
Every GCLK and RCLK network has its own clock control block. The control block provides the following features:
■■■
Clock source selection (dynamic selection for GCLKs)GCLK multiplexing
Clock power down (static or dynamic clock enable or disable)
Figure5–12 shows the GCLK select blocks for ArriaII devices. Figure5–12.GCLK Control Block for Arria II Devices
CLKPinPLL CounterOutputs (3)CLKSELECT[1..0](1)222CLKPinInter-TransceiverBlock Clock Lines(4)InternalLogicStatic ClockSelect (2)This multiplexersupports user-controllabledynamic switchingEnable/DisableInternalLogicGCLKNotes to Figure5–12:
(1)You can only dynamically control these clock select signals through internal logic when the device is operating in user
mode.(2)These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
controlled during user mode operation.(3)The left side of the ArriaII GX device only allows PLL counter outputs as the dynamic clock source selection to the
GCLK network.(4)This is only available on the left side of the ArriaII GX device.
Select the clock source for the GCLK control block either statically with a setting in the QuartusII software or dynamically with an internal logic to drive the multiplexer select inputs. When selecting the clock source dynamically, you can either select two PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX95EF35I3N中文规格书 - 图文
