7Series FPGAs Package Files
About ASCII Package Files
The ASCII files for each package include a comma-separated-values (CSV) version and a text version optimized for a browser or text editor. Each of the files consists of the following:??
Device/Package name (FPGA Family—Device—Package), date and time of creationEight columns containing data for each pin:
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Pin—Pin location on the package.Pin Name—The name of the assigned pin.
Memory Byte Group—Memory byte group between 0 and 3. For more information on the memory byte group, see the 7Series FPGAs Memory Interface Solutions User Guide (UG586).Bank—Bank number.
VCCAUX Group—Number corresponding to the VCCAUX_IO power supply for the given pin. VCCAUX is shown for packages with only one VCCAUX group.
Super Logic Region—Number corresponding to the super logic region (SLR) in the devices implemented with stacked silicon interconnect (SSI) technology.I/O Type—CONFIG, HR, HP, or GT (GTP, GTX, GTH) depending on the
I/O type. For more information on the I/O type, see the 7Series FPGAs SelectIO Resources User Guide (UG471).
No-Connect—This list of devices is used for migration between devices that have the same package size and are not connected at that specific pin.
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Total number of pins in the package.
The package file links for the ruggedized packages have the same pinouts are as theequivalent BGA packages.
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RS pinouts use the SBG/SBV files (Artix?-7 devices)RB pinouts use the FBG/FBV files (Artix-7 devices)
RF pinouts use the FFG/FFV files (Kintex?-7 and Virtex?-7 devices)
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 2:7Series FPGAs Package Files
Table 2-1:Device
XC7S6XA7S6XC7S15XA7S15XC7S25XA7S25XC7S50XA7S50XC7S75XA7S75XC7S100XA7S100
Spartan-7 FPGAs Package/Device Pinout Files
CPGA196
CPGA196ProductionCPGA196Production
CSGA225
CSGA225ProductionCSGA225ProductionCSGA225Production
CSGA324FTGB196
FTGB196ProductionFTGB196Production
FGGA484FGGA676
CSGA324ProductionCSGA324Production
FTGB196ProductionFTGB196Production
FGGA484ProductionFGGA484ProductionFGGA484Production
FGGA676ProductionFGGA676Production
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 2:7Series FPGAs Package Files
To download all available Virtex-7 FPGAs package/device/pinout files click here:
Note:Only the available files listed in Table2-4 and Table2-5 are linked and consolidated in the
above ZIP file.
Table 2-4:Device
XC7V585TXC7V2000TXQ7V585T
Virtex-7T FPGAs Package/Device Pinout Files
FF1157/FFG1157FF1761/FFG1761FL1925/FLG1925FH1761/FHG1761RF1157
FFG1157
FFG1761
FLG1925
FHG1761
RF1157
RF1761
RF1761
Table 2-5:Device
XC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690TXC7VX980T
Virtex-7XT FPGAs Package/Device Pinout FilesFF1157FFG1157FFV1157RF1157
FFG1157FFG1157FFG1157
FFG1158FFG1158FFG1158
FFG1157
FFG1158
FFG1761
FFG1926FFG1926
FFG1761
FF1158FFG1158FFV1158RF1158FF1761
FF1927FF1930
FFG1761FF1926FFG1927FF1928FFG1930FL1926FL1928FL1930FFV1761FFG1926FFG1928FLG1926FLG1928FLG1930
FFV1927RF1930RF1761
FFG1761
FFG1927FFG1927FFG1927FFG1927
FFG1928
FFG1930FFG1930
FLG1926
FLG1928
FLG1930
FFG1930
XC7VX1140TXQ7VX330TXQ7VX485TXQ7VX690TXQ7VX980T
RF1157
RF1158
RF1157
RF1761RF1761RF1761
RF1930RF1930RF1930
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50TCPG236 Package (only)—XA7A15T, XA7A35T, and XA7A50T
X-Ref Target - Figure 3-411ABCDEFGHJKLMNPRTUVW1EVE2345678910111213141516171819JLSSSSABCsBBDEFVGKCVEVEEGHJBKLMNPRT2PYD01BsUBUVWO2345678M9I10111213141516171819User I/O PinsIO_LXXY_#sIO_XX_#Transceiver PinsEVVMGTAVCC_G#MGTAVTT_G#MGTVCCAUX_G#MGTAVTTRCALMGTRREFMGTREFCLK1/0PMGTREFCLK1/0NMGTPRXPMGTPRXNMGTPTXPMGTPTXNY012PKIOMDJLCDedicated PinsCCLK_0CFGBVS_0DONE_0DXP_0DXN_0GNDADC_0INIT_B_0M0_0M1_0M2_0PROGRAM_B_0TCK_0TDI_0TDO_0TMS_0VCCADC_0VCCBATT_0nSSSSVP_0VN_0VREFP_0VREFN_0Other PinsGNDVCCAUX_IO_G#VCCAUXVCCINTVCCO_#VCCBRAMNCMulti?Function PinsBBBBBBBBUrADV_BFCS_BFOE_BMOSIFWE_BDOUT_CSO_BCSI_BPUDC_BRDWR_BRS0?RS1AD0P/AD0N?AD15P/AD15NEMCCLKVRNVRPVREFD00?D31A00?A28DQSMRCCSRCCFigure 3-41:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50TCPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Pinout Diagram
X-Ref Target - Figure 3-42VGug475_c3_301_0117141ABC2216216342162165621621678216216910111213141516171819216216161616161616161616161616141414141414ABCDEFGHJKL216D216216EFGHJKL35353535353535353535353514141414141414141414141414M353535NPRTUVW135353535353434343434343434343434343434343434341414M14141414141414141414141414141414141414141414NPRTUV3434343434342345678914141414141414W10111213141516171819ug475_c3_302_011714Figure 3-42:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T I/O Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
X-Ref Target - Figure 3-431ABCDEFGHJKL2345678910111213141516171819161616161616161616161616141414141414ABCDEFGHJKL35353535353535353535353514141414141414141414141414M353535NPRTUVW135353535353434343434343434343434343434343434341414M14141414141414141414141414141414141414141414NPRTUV3434343434342345678914141414141414W10111213141516171819Memory Groupings Pins##########HP I/OHR I/OHP I/O ? VCCAUX Group 0HP I/O ? VCCAUX Group 1HP I/O ? VCCAUX Group 2HP I/O ? VCCAUX Group 3HP I/O ? VCCAUX Group 4HP I/O ? VCCAUX Group 5HP I/O ? VCCAUX Group 6HP I/O ? VCCAUX Group 7#######DQS pinHP DCI pin or HR I/OMemory Byte Group 0Memory Byte Group 1Memory Byte Group 2Memory Byte Group 3Bank Numberug475_c3_303_013014Figure 3-43:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50TCPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Memory Groupings
X-Ref Target - Figure 3-441ABCDEFGHJKLMNPRTUVW13434352345678910111213141516171819A161616BCDE14016FGH3535353535343434141414141414JKLMNP14RT14UVW3402345678910111213141516171819Power Pins#VCCO_#VCCINTVCCAUX#VCCAUX_IO_G#VCCBRAMVCCBATT_0VCCADC_0GNDADC_0###MGTVCCAUXMGTVCCAUX_G# or MGTHVCCAUX_G#MGTAVCCMGTAVCC_G# or MGTHAVCC_G#MGTAVTTMGTAVTT_G# or MGTHAVTT_G#GNDug475_c3_304_011714Figure 3-44:CP236 and CPG236 Packages—XC7A15T, XC7A35T, and XC7A50T
CPG236 Packages (only)—XA7A15T, XA7A35T, and XA7A50T Power and GND Placement
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
FPGA可编程逻辑器件芯片XCZU28DR-2FFVG1517E中文规格书 - 图文
