FPGA可编程逻辑器件芯片XC2V80-6CS144I中文规格书 - 图文

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Generating PROM Files

PROM files are generated from bitstream files with the PROMGen utility. Users can access PROMGen directly from the command line or indirectly through the iMPACT File

Generation Mode. For PROMGen syntax, refer to the Development System Reference Guide. For information on iMPACT, refer to the ISE? Software Documentation). PROM files serve to reformat bitstream files for PROM programming and combine bitstream files for serial daisy chains (see “PROM Files for Serial Daisy Chains”).

PROM Files for Serial Daisy Chains

Configuration data for serial daisy chains requires special formatting because separate BIT files cannot simply be concatenated together to program the daisy chain. The special formatting is performed by PROMGen (or iMPACT) when generating a PROM file from multiple bitstreams. To generate the PROM file, specify multiple bitstreams using the PROMGen -n, -u, and -d options or the iMPACT File Generation Wizard. Refer to software documentation for details.

PROMGen reformats the configuration bitstreams by nesting downstream configuration data into configuration packets for upstream devices. Attempting to program the chain by sending multiple bitstreams to the first device causes the first device to configure and then ignore the subsequent data.

PROM Files for SelectMAP Configuration

The MCS file format is most commonly used to program Xilinx configuration PROMs that in turn program a single FPGA in SelectMAP mode. For custom configuration solutions, the BIN and HEX files are the easiest PROM file formats to use due to their raw data format. In some cases, additional formatting is required; refer to XAPP502, Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode for details.

If multiple configuration bitstreams for a SelectMAP configuration reside on a single

memory device, the bitstreams must not be combined into a serial daisy chain PROM file. Instead, the target memory device should be programmed with multiple BIN or HEX files. If a single PROM file with multiple, separate data streams is needed, one can be generated in iMPACT by targeting a Parallel PROM, then selecting the appropriate number of data streams. This can also be accomplished through the PROMGen command line. Refer to PROMGen software documentation for details.

For Platform Flash XL-based SelectMAP configuration, use the iMPACT software to

generate an MCS PROM file. Select the Xilinx XCF128X device as the target PROM device type for creating the file. See UG438, Platform Flash XL User Guide, for PROM file generation instructions.

PROM Files for SPI/BPI Configuration

The -d and -u options in PROMGen or the iMPACT File Generation Wizard are used to create PROM files for third-party Flash devices. The output format supported by your third-party programmer should be chosen. Some BPI devices require endian-swapping to be enabled when programming the PROM file. Refer to the Flash vendor's documentation.

Bit Swapping

Bit swapping is the swapping of the bits within a byte. The MCS, EXO, and TEK PROM file formats are always bit swapped. The HEX file format can be bit swapped or not bit

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024

Chapter 1:Configuration Overview

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2024

Chapter 2:Configuration Interfaces

Table 2-5:ABORT Status Word

Bit Number

Status Bit NameCFGERR_B

Meaning

Configuration error (active Low)

0 = A configuration error has occurred.1 = No configuration error.Sync word received (active High)

DALIGN

0 = No sync word received.

1 = Sync word received by interface logic.Readback in progress (active High)

RIP

0 = No readback in progress.1 = A readback is in progress.ABORT in progress (active Low)

D4D3-D0

IN_ABORT_B

1111

0 = Abort is in progress.1 = No abort in progress.Fixed to ones.

The ABORT sequence lasts four CCLK cycles. During those cycles, the status word changes to reflect data alignment and ABORT status. A typical sequence might be:

11011111110011111000111110011111

=>=>=>=>

DALIGN = 1,DALIGN = 1,DALIGN = 0,DALIGN = 0,

IN_ABORT_B = 1 IN_ABORT_B = 0 IN_ABORT_B = 0 IN_ABORT_B = 1

After the last cycle, the synchronization word can be reloaded to establish data alignment.

Resuming Configuration or Readback After an Abort

There are two ways to resume configuration or readback after an ABORT: ??

The device can be resynchronized after the ABORT completes.The device can be reset by pulsing PROGRAM_B Low at any time.

To resynchronize the device, CS_B must be deasserted then reasserted. Configuration or readback can be resumed by sending the last configuration or readback packet that was in progress when the ABORT occurred. Alternatively, configuration or readback can be restarted from the beginning.

SelectMAP Reconfiguration

The term reconfiguration refers to reprogramming an FPGA after its DONE pin has gone High. Reconfiguration can be initiated by pulsing the PROGRAM_B pin (this method is identical to configuration) or by resynchronizing the device and sending configuration data.

To reconfigure a device in SelectMAP mode without pulsing PROGRAM_B, the BitGen persist option must be set—otherwise, the DATA pins become user I/O after

configuration. The persist option must also be selected for the new bitstream reconfiguring the device. In SelectMAP x32 mode, the RS[1:0], CSO_B, and A[19:16] pins are not available for User mode when persist is on. In SelectMap x8 and x16 modes, RS[1:0] and CSO_B are not available for User mode when persist is on. Reconfiguration must be enabled in

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2024

SelectMAP Configuration Interface

BitGen. By default, the SelectMAPx8 interface (D0–D7) is preserved unless another SelectMAP width has been selected with the CONFIG_MODE constraint.

Reconfiguration begins when the synchronization word is clocked into the SelectMAP port. The remainder of the operation is identical to configuration as described above.

SelectMAP Data Ordering

In many cases, SelectMAP configuration is driven by a user application residing on a microprocessor, CPLD, or in some cases another FPGA. In these applications, it is

important to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA.

In SelectMAP x8 mode, configuration data is loaded at one byte per CCLK, with the MSB of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from many other devices. For x16 and x32 modes, see “Parallel Bus Bit Order.” This convention can be a source of confusion when designing custom configuration solutions. Table2-6 shows how to load the hexadecimal value 0xABCD into the SelectMAP data bus. Table 2-6:Bit Ordering for SelectMAP 8-Bit ModeCCLK Cycle

Notes:

1.D[0:7] represent the SelectMAP DATA pins.

Hex Equivalent

0xAB0xCD

D011

D101

D210

D300

D411

D501

D610

D711

Some applications can accommodate the non-conventional data ordering without

difficulty. For other applications, it can be more convenient for the source configuration data file to be bit swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate bit-swapped PROM files (see “Configuration Data File Formats”).

Figure2-19 shows the bit ordering for x8, x16, and x32 modes. It also shows the bit ordering for Virtex-4 FPGA x32 mode.

Virtex-5 Modex32x16x8

3130292827262524232221202418171615141312111024252627282930311617181920242223

7000

6111

5222

4333

3444

2555

1666

0777

101112131415101112131415