SelectMAP Configuration Interface
BitGen. By default, the SelectMAPx8 interface (D0–D7) is preserved unless another SelectMAP width has been selected with the CONFIG_MODE constraint.
Reconfiguration begins when the synchronization word is clocked into the SelectMAP port. The remainder of the operation is identical to configuration as described above.
SelectMAP Data Ordering
In many cases, SelectMAP configuration is driven by a user application residing on a microprocessor, CPLD, or in some cases another FPGA. In these applications, it is
important to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA.
In SelectMAP x8 mode, configuration data is loaded at one byte per CCLK, with the MSB of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from many other devices. For x16 and x32 modes, see “Parallel Bus Bit Order.” This convention can be a source of confusion when designing custom configuration solutions. Table2-6 shows how to load the hexadecimal value 0xABCD into the SelectMAP data bus. Table 2-6:Bit Ordering for SelectMAP 8-Bit ModeCCLK Cycle
12
Notes:
1.D[0:7] represent the SelectMAP DATA pins.
Hex Equivalent
0xAB0xCD
D011
D101
D210
D300
D411
D501
D610
D711
Some applications can accommodate the non-conventional data ordering without
difficulty. For other applications, it can be more convenient for the source configuration data file to be bit swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate bit-swapped PROM files (see “Configuration Data File Formats”).
Figure2-19 shows the bit ordering for x8, x16, and x32 modes. It also shows the bit ordering for Virtex-4 FPGA x32 mode.
Virtex-5 Modex32x16x8
Pin
3130292827262524232221201918171615141312111024252627282930311617181920212223
88
99
9
8
7000
6111
5222
4333
3444
2555
1666
0777
101112131415101112131415
Virtex-4x32 Mode
31302928272625242322212019181716151413121110
9
8
7
6
5
4
3
2
1
0
Figure 2-19:Bit Ordering
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Board Layout for Configuration Clock (CCLK)
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2V80-4CS144I中文规格书
