MultiTrack Interconnect
C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross
M-RAM blocks and also drive to row and column interconnects at everyfourth LAB. C16 interconnects drive LAB local interconnects via C4 andR4 interconnects and do not drive LAB local interconnects directly. Allembedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSPblocks) connects to row and column interconnects and has local
interconnect regions driven by row and column interconnects. Theseblocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks,labclk[5..0].
Table2–18 shows the StratixII GX device’s routing scheme.
Table2–18. StratixII GX Device Routing Scheme(Part 1 of2)
Destination
Shared Arithmetic ChainDirect Link InterconnectLocal InterconnectM512 RAM BlockR24 InterconnectC16 InterconnectM4K RAM BlockR4 InterconnectC4 InterconnectRegister ChainM-RAM BlockCarry ChainColumn IOEDSP BlocksShared arithmetic chainCarry chainRegister chainLocal interconnectDirect link interconnectR4 interconnectR24 interconnectC4 interconnectC16 interconnectALM
M512 RAM blockM4K RAM blockM-RAM blockDSP blocks
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Stratix II GX Device Handbook, Volume 1
ALMSource
Row IOEStratix II GX Architecture
Table2–18. StratixII GX Device Routing Scheme(Part 2 of2)
Destination
Shared Arithmetic ChainDirect Link InterconnectLocal InterconnectM512 RAM BlockR24 InterconnectC16 InterconnectM4K RAM BlockR4 InterconnectC4 InterconnectRegister ChainM-RAM BlockCarry ChainColumn IOEDSP BlocksColumn IOERow IOE
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TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table2–19 shows the size and features of the different RAM blocks.
Table2–19.TriMatrix Memory Features(Part 1 of2)
Memory Feature
Maximum performance True dual-port memorySimple dual-port memorySingle-port memoryShift registerROMFIFO bufferPack modeByte enable
Address clock enableParity bitsMixed clock modeMemory initialization (.mif)
M512 RAM Block (32×18 Bits)
500 MHz
M4K RAM Block (128×36 Bits)
550 MHz
ALMSource
M-RAM Block(4K×144Bits)
420 MHz
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Stratix II GX Device Handbook, Volume 1
Row IOETriMatrix Memory
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M-RAM block registers (renwe, address, byte enable, datain, and output registers). The output register can be bypassed. The six
labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure2–53.
Figure2–53.M-RAM Block Control Signals
DedicatedRow LABClocksLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectclock_aclocken_aaclr_arenwe_arenwe_baclr_bclocken_bclock_b6LocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectLocalInterconnectThe R4, R24, C4, and direct link interconnects from adjacent LABs on either the right or left side drive the M-RAM block local interconnect. Up to 16 direct link input connections to the M-RAM block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M-RAM block outputs can also connect to left and right LABs
through direct link interconnect. Figure2–54 shows an example floorplan for the EP2SGX130 device and the location of the M-RAM interfaces. Figures2–55 and 2–56 show the interface between the M-RAM block and the logic array.
Stratix II GX Device Handbook, Volume 1
PLLs and Clock Networks
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Stratix II GX Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP2SGX60DF780C4中文规格书 - 图文
