Asynchronous Interface Bus Operation
The bus on the device is multiplexed. Data I/O, addresses, and commands all share thesame pins. I/O[15:8] are used only for data in the x16 configuration. Addresses andcommands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, address inputcycles, and one or more data cycles, either READ or WRITE.
Table 4: Asynchronous Interface Mode Selection
Mode1Standby2Command inputAddress inputData inputData outputWrite protectNotes:
CE#HLLLLXCLEXHLLLXALEXLHLLXHXXWE#XRE#XHHHI/OxXXXXXXWP#0V/VCCHHHXL1.Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
2.WP# should be biased to CMOS LOW or HIGH for standby.
Asynchronous Enable/Standby
When the device is not performing an operation, the CE# pin is typically driven HIGHand the device enters standby mode. The memory will enter standby if CE# goes HIGHwhile data is being transferred and the device is not busy. This helps reduce power con-sumption.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-chronous memory bus as other Flash or SRAM devices. Other devices on the memorybus can then be accessed while the NAND Flash is busy with internal operations. Thiscapability is important for designs that require multiple NAND Flash devices on thesame bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signalsignifies that an ADDRESS INPUT cycle is occurring.
Asynchronous Commands
An asynchronous command is written from I/O[7:0] to the command register on the ris-ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, somecommands, including READ STATUS (70h), are accepted by die (LUNs) even when theyare busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a commandis issued.
PDF: 09005aef83e5ffed
m68a_1gb_nand.pdf - Rev. L 10/12 EN
1Gb x8, x16: NAND Flash Memory
Feature Operations
Table 11: Feature Addresses 01h: Timing Mode
SubfeatureParameterP1Timing modeMode 0(default)Mode 1Mode 2Mode 3Mode 4Mode 5P2Reserved (0)P3Reserved (0)P4Reserved (0)00h00h00hReserved (0)Reserved (0)Reserved (0)Reserved (0)Reserved (0)Reserved (0)00001100110001010100h01h02h03h04h05h1, 222334OptionsI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0ValueNotesPDF: 09005aef83e5ffed
m68a_1gb_nand.pdf - Rev. L 10/12 EN
1Gb x8, x16: NAND Flash Memory
Feature Operations
Table 12: Feature Addresses 80h: Programmable I/O Drive Strength
SubfeatureParameterP1I/O drive strengthFull (default)Three-quartersOne-halfOne-quarterP2Reserved (0)P3Reserved (0)P4Reserved (0)Note:
00h00h00hReserved (0)Reserved (0)Reserved (0)Reserved (0)0011010100h01h02h03h1OptionsI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0ValueNotes1.The programmable drive strength feature address is used to change the default I/O
drive strength. Drive strength should be selected based on expected loading of thememory bus. This table shows the four supported output drive strength settings. Thedefault drive strength is full strength. The device returns to the default drive strengthmode when the device is power cycled. AC timing parameters may need to be relaxed ifI/O drive strength is not set to full.
Table 13: Feature Addresses 81h: Programmable R/B# Pull-Down Strength
SubfeatureParameterP1R/B# pull-downstrengthFull (default)Three-quartersOne-halfOne-quarterP2Reserved (0)P3Reserved (0)P4Reserved (0)Note:
00h00h00h0011010100h01h02h03h1OptionsI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0ValueNotes1.This feature address is used to change the default R/B# pull-down strength. Its strength
should be selected based on the expected loading of R/B#. Full strength is the default,power-on value.
PDF: 09005aef83e5ffed
m68a_1gb_nand.pdf - Rev. L 10/12 EN
1Gb x8, x16: NAND Flash Memory
Status Operations
Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same targetthrough its 8-bit status register.
After the READ STATUS (70h) command is issued, status register output is enabled. Thecontents of the status register are returned on I/O[7:0] for each data output request.When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it isnot necessary to toggle RE# to see the status register update.
While monitoring the status register to determine when a data transfer from the Flasharray to the data register (tR) is complete, the host must issue the READ MODE (00h)command to disable the status register and enable data output (see Read Operations).With internal ECC enabled, a READ STATUS command is required after completion ofthe data transfer (tR_ECC) to determine whether an uncorrectable read error occurred.
Table 14: Status Register Definition
SR Bit76543Program PageProgram PageCache ModeWrite protectRDYARDY––Write protectRDY1 cacheARDY2––Page ReadWrite protectRDYARDY–Rewriterecommended3–ReservedFAIL4Page Read Cache ModeWrite protectRDY1 cacheARDY2––Block EraseDescriptionWrite protect0 = Protected1 = Not protectedRDYARDY––0 = Busy1 = ReadyDon't CareDon't Care0 = Normal or uncorrecta-ble1 = Rewrite recommendedDon't CareDon't Care0 = Successful PROGRAM/ERASE/READ1 = Error in PROGRAM/ERASEREAD210–FAILC (N - 1)FAIL–FAILC (N - 1)FAIL (N)–––––FAILNotes:
1.Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.2.Status register bit 5 is 0 during the actual programming operation. If cache mode is
used, this bit will be 1 when all internal operations are complete.
3.A status register bit defined as Rewrite Recommended signifies that the page includes
acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-writeof this page is recommended. (Up to a 4-bit error has been corrected if internalECC was enabled.)
4.A status register bit defined as FAIL signifies that an uncorrectable READ error has oc-curred.
PDF: 09005aef83e5ffed
m68a_1gb_nand.pdf - Rev. L 10/12 EN
1Gb x8, x16: NAND Flash Memory
Column Address Operations
Column Address Operations
The column address operations affect how data is input to and output from the cacheregisters within the selected die (LUNs). These features provide host flexibility for man-aging data, especially when the host internal buffer is smaller than the number of databytes or words in the cache register.
When the asynchronous interface is active, column address operations can address anybyte in the selected cache register.
RANDOM DATA READ (05h-E0h)
The RANDOM DATA READ (05h-E0h) command changes the column address of the se-lected cache register and enables data output from the last selected die (LUN). Thiscommand is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). Itis also accepted by the selected die (LUN) during CACHE READ operations(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles containingthe column address, followed by the E0h command, puts the selected die (LUN) intodata output mode. After the E0h command cycle is issued, the host must wait at leasttWHR before requesting data output. The selected die (LUN) stays in data output modeuntil another valid command is issued.
Figure 31: RANDOM DATA READ (05h-E0h) Operation
Cycle type
DOUTDOUTCommandtRHWAddressAddressCommandtWHRDOUTDOUTDOUTI/O[7:0]DnDn +105hC1C2E0hDkDk + 1Dk + 2SR[6]
PDF: 09005aef83e5ffed
m68a_1gb_nand.pdf - Rev. L 10/12 EN
MEMORY存储芯片MT29F256G08AUCABH3-10A中文规格书 - 图文
