width. Table1-5 shows an example bitstream with an inserted bus width detection pattern. When observing the pattern on the FPGA data pin, the bits are bit swapped, as described in “Parallel Bus Bit Order.”
The bitstream data in Table1-5 shows the 32-bit configuration word for an unswapped bitstream. For a swapped bitstream format, the LSB and MSB order for the individual bytes are swapped. For example, the Sync word at the FPGA pins in the D[31:00] bit order would be: 0x5599AA66. For swapped and unswapped formats see “Configuration Data File Formats.”.
Table 1-5:Bus Width Detection Pattern
D[24:31]0xFF0x000x110xFF0xFF0xAA…
D[16:23]0xFF0x000x220xFF0xFF0x99…
D[8:15]0xFF0x000x000xFF0xFF0x55…
D[0:7]0xFF0xBB0x440xFF0xFF0x66…
Sync Word…
Bus Width PatternBus Width Pattern
Comments
Bus width auto detection is transparent to most users, because all configuration bitstreams (BIT or RBT files) generated by the Xilinx ISE? Bitstream Generator (BitGen) software include the Bus Width Auto Detection pattern. These patterns are ignored by the
configuration logic if the Mode pins are set to Master Serial, Slave Serial, JTAG, or SPI mode.
For the x8 bus, the configuration bus width detection logic first finds 0xBB on the D[0:7] pins, followed by 0x11. For the x16 bus, the configuration bus width detection logic first finds 0xBB on D[0:7] followed by 0x22. For the x32 bus, the configuration bus width detection logic first finds 0xBB, on D[0:7], followed by 0x44.
If the immediate byte after 0xBB is not 0x11, 0x22, or 0x44, the bus width state machine is reset to search for the next 0xBB until a valid sequence is found. Then it switches to the appropriate external bus width and starts looking for the Sync word.
Sync Word
A special Sync word is used to allow configuration logic to align at a 32-bit word boundary. No packet processed by the FPGA until the Sync word is found. The bus width must be detected successfully for parallel configuration modes before the Sync word can be detected. Table1-6 shows the Sync word in an unswapped bitstream format.Table 1-6:Sync Word
31:240xAA
23:160x99
15:80x55
7:00x66
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Generating PROM Files
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Chapter 2:Configuration Interfaces
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Sending a bitstream to the data pin follows the same bit-swapping rule as inSelectMAP mode. See “Parallel Bus Bit Order.”
If Flash programming is not required, FCS_B, FOE_B, and FWE_B can be tied off; thatis, DONE is connected to FCS_B, FOE_B is tied Low, and FWE_B is tied High.The CCLK outputs are not used to connect to Flash but are used to sample Flash readdata during configuration. All timings are referenced to CCLK. The CCLK pin mustnot be driven or tied High or Low.
The RS[1:0] pins are not connected as shown in Figure2-22. These output pins areonly required for MultiBoot configuration. See Chapter8, “Reconfiguration andMultiBoot.”
HSWAPEN must be connected to either disable or enable the pull-up resistors.If HSWAPEN is left unconnected or tied High, a pull-up resistor is required forFCS_B.
If HSWAPEN is tied Low, the FCB_B, FOE_B, FWE_B, and the address pins haveinternal weak pull-up resistors during configuration. After configuration, FCS_B canbe either controlled by I/O in user mode or by enabling a weak pull-up resistorthrough constraints.
To enable the active driver on DONE, the DriveDONE option in BitGen must beenabled.
“MultiBoot Bitstream Spacing,” page155 provides information on when DCI or DCMlock wait is turned on.
For daisy chaining FPGAs in BPI mode, see Figure2-12, page52.
The BPI Flash vendor data sheet should be referred to for details on the specific Flashsignal connectivity. To prevent address misalignment, close attention should be paidto the Flash family address LSB for the byte/word mode used. Not all Flash familiesuse the A0 as the address LSB.
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Table2-9 defines the BPI configuration interface pins.
If the FPGA is subject to reprogramming or fallback during configuration from the BPI flash, then the INIT pin can be connected to the BPI reset to set the BPI into a known state.
Table 2-9:
Virtex-5 Device BPI Configuration Interface Pins
Type Input
Dedicated or Dual-Purpose
010 = BPI-Up mode011 = BPI-Down mode
HSWAPEN
Input
Dedicated
Controls I/O (except Bank 0 dedicated I/Os) pull-up resistors during configuration. This pin has a built-in weak pull-up resistor.0 = Pull-up during configuration1 = 3-state during configuration
DONE
Bidirectional, Dedicated Active-High signal indicating configuration is complete: Open-Drain, 0 = FPGA not configured or Active
1 = FPGA configured
Description
Pin Name M[2:0]
Dedicated The Mode pins determine the BPI mode:
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Byte Peripheral Interface Parallel Flash Mode
Table 2-9:Virtex-5 Device BPI Configuration Interface Pins (Continued)
Type
Dedicated or Dual-Purpose
Description
Pin Name INIT_B
Input or Dedicated Before the Mode pins are sampled, INIT_B is an input that can be held Output, Low to delay configuration. After the Mode pins are sampled, INIT_B Open-Drain is an open-drain, active-Low output indicating whether a CRC error
occurred during configuration:
0 = CRC error 1 = No CRC error
When the SEU detection function is enabled, INIT_B is optionally driven Low when a read back CRC error is detected.
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset
CCLK Output
Dedicated Configuration clock output. CCLK does not directly connect to BPI
Flash but is used internally to generate the address and sample read data. Dual
Active-Low Flash chip select output. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash output enable. This output is actively driven Low during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Active-Low Flash write enable. This output is actively driven High during configuration and 3-stated after configuration. It has a weak pull-up resistor during configuration. By default, this signal has a weak pull-down resistor after configuration.
Address output. For I/O bank locations, see Table1-2, page17.
FCS_BOutput
FOE_B Output Dual
FWE_BOutputDual
ADDR[25:0]OutputDual
D[15:0]InputDual
Data input, sampled by the rising edge of the FPGA CCLK. For I/O bank location, see Table1-2, page17.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2S30-5FG456C中文规格书 - 图文
