TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005I/O Supply
DVDDSchottkyDiodeCore SupplyC6000DSPCVDDVSSGND
Figure 11. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimizeinductance and resistance in the power delivery path. Additionally, when designing for high-performanceapplications utilizing the C6000? platform of DSPs, the PC board should include separate power planes forcore, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
power-supply decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possibleclose to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supplyand 30 for the I/O supply. These caps need to be close to the DSP power pins, no more than 1.25 cm maximumdistance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasiticinductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closestto the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small package) should benext closest. TI recommends no less than 8 small and 8 medium caps per supply (32 total) be placedimmediately next to the BGA vias, using the “interior” BGA space and at least the corners of the “exterior”.Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on theorder of 100 μF) should be furthest away (but still as close as possible). No less than 4 large caps per supply(8 total) should be placed outside of the BGA.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of anycomponent, verification of capacitor availability over the product’s production lifetime should be considered.
TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN for ?5E0 devices??§ (see Figure 16)
NONO.
?5E0
A?5E0
PLL MODE x12MIN
12345
??
PLL MODE x6MIN13.30.4C0.4C
MAX33.3
x1 (BYPASS)MIN13.30.45C0.45C5
10.02CMAX33.3
UNIT
MAX33.3
tc(CLKIN)tw(CLKINH)tw(CLKINL)tt(CLKIN)tJ(CLKIN)
Cycle time, CLKINPulse duration, CLKIN highPulse duration, CLKIN lowTransition time, CLKINPeriod jitter, CLKIN
240.4C0.4C
nsnsnsnsns
50.02C
0.02C
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
timing requirements for CLKIN for -6E3 devices??§ (see Figure 16)
?6E3, A?6E3
NO.12345
??
PLL MODE x12MIN
tc(CLKIN)tw(CLKINH)tw(CLKINL)tt(CLKIN)tJ(CLKIN)
Cycle time, CLKINPulse duration, CLKIN highPulse duration, CLKIN lowTransition time, CLKINPeriod jitter, CLKIN
200.4C0.4C
50.02CMAX33.3
PLL MODE x6MIN13.30.4C0.4C
50.02CMAX33.3
x1 (BYPASS)MIN13.30.45C0.45C
10.02CMAX33.3
UNITnsnsnsnsns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
timing requirements for CLKIN for -7E3 devices??§ (see Figure 16)
?7E3
NO.12345
??
PLL MODE x12MIN
tc(CLKIN)tw(CLKINH)tw(CLKINL)tt(CLKIN)tJ(CLKIN)
Cycle time, CLKINPulse duration, CLKIN highPulse duration, CLKIN lowTransition time, CLKINPeriod jitter, CLKIN
16.60.4C0.4C
50.02CMAX33.3
PLL MODE x6MIN13.30.4C0.4C
50.02CMAX33.3
x1 (BYPASS)MIN13.30.45C0.45C
10.02CMAX33.3
UNITnsnsnsnsns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
52CLKIN
3414Figure 16. CLKIN Timing
MEMORY存储芯片TMS320C6727BZDH250中文规格书
