SIII52001-2.1
Electrical Characteristics
Operating Conditions
When Stratix?III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of StratixIII devices, system designers must consider the operating requirements discussed in this chapter. StratixIII devices are offered in both
commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speedgrades.
1
In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with “C” prefix and industrial with “I” prefix.
Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for StratixIII devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Conditions beyond those listed in Table1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.
Table1–1.StratixIII Device Absolute Maximum Ratings (Note1)(Part 1 of 2)
SymbolVCCLVCCVCCD_PLLVCCA_PLLVCCPTVCCPGMVCCPDVCCIOVCC_CLKINVCCBATVI
Parameter
Selectable core voltage power supplyI/O registers power supplyPLL digital power supplyPLL analog power supply
Programmable power technology power supplyConfiguration pins power supplyI/O pre-driver power supplyI/O power supply
Differential clock input power supply (top and bottom I/O banks only)
Battery back-up power supply for design security volatile key registerDC Input voltage
Minimum-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5-0.5
Maximum1.651.651.653.753.753.93.93.93.753.754.0
UnitVVVVVVVVVVV
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–66.EP3SL110 Row Pins output Timing Parameters (Part 2 of 4)
ParameterI/O Standard
Current StrengthFast ModelIndustrial
Commercial
C2VCCL=1.1V
C3VCCL=1.1V
C4VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3VCCL=1.1V
I4VCCL=1.1V
VCCL=1.1V
I4LVCCL=0.9V
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
ClockGCLK
2mA
GCLK PLLGCLK
4mA
GCLK PLLGCLK
6mA
GCLK PLLGCLK
8mA
GCLK PLLGCLK
2mA
GCLK PLLGCLK
4mA
GCLK PLLGCLK
6mA
GCLK PLLGCLK
8mA
GCLK PLLGCLK
2mA
GCLK PLLGCLK
4mA
GCLK PLLGCLKGCLK PLLGCLK
12mA
GCLK PLLGCLK
16mA
GCLK PLL
tcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotco
3.4381.6703.2131.4453.1481.3803.0881.3203.3491.5813.1071.3393.0801.3123.0711.3033.2921.5243.1121.3443.0311.2663.0261.2543.0171.238
3.7061.8793.5041.6773.4021.5753.3281.5013.6241.7973.3661.5393.3191.4923.3101.4833.5491.7223.3601.5333.2741.4433.2621.4313.2441.413
5.2985.7476.3036.1776.4395.8886.4456.3186.5382.5212.6722.9322.9522.9372.7933.0563.0752.9494.9715.3785.8985.7726.0345.5236.0395.9116.1312.1942.3032.5272.5472.5322.4282.6502.6682.5424.8185.2285.7395.6135.8755.3555.8665.7395.9592.0412.1532.3682.3882.3732.2602.4772.4962.3704.7415.1345.6425.5165.7785.2605.7725.6455.8651.9642.0592.2712.2912.2762.1652.3832.4022.2765.2085.6606.2316.1056.3675.7956.3696.2426.4622.4312.5852.8602.8802.8652.7002.9802.9992.8734.8035.2235.7405.6145.8765.3495.8655.7385.9582.0262.1482.3692.3892.3742.2542.4762.4952.3694.7305.1275.6345.5085.7705.2515.7605.6335.8531.9532.0522.2632.2832.2682.1562.3712.3902.2644.7085.1095.6155.4895.7515.2335.7385.6115.8311.9312.0342.2442.2642.2492.1382.3492.3682.2425.1185.5746.1566.0306.2925.7076.2856.1586.3782.3412.4992.7852.8052.7902.6122.8962.9152.7894.8255.2515.7815.6555.9175.3745.9075.7806.0002.0482.1762.4102.4302.4152.2792.5182.5372.4114.6295.0135.4785.3795.6165.1175.5975.4985.6921.8471.9332.1292.1492.1372.0332.2302.2492.1264.6215.0055.4765.3715.6145.1165.5965.4915.6911.8391.9252.1212.1412.1292.0252.2232.2422.1194.5964.9805.4595.3445.5975.0995.5785.4645.6731.8141.9002.0942.1142.1021.9992.1962.2152.092
1.8 V
1.5 V
1.2 V
SSTL-2 CLASS I
8mA
SSTL-2 CLASSII
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–98 specifies EP3SL340 row pins input timing parameters for differential I/O standards.
Table1–98.EP3SL340 Row Pins Input Timing Parameters (Part 1 of 2)
ParameterFast ModelIndustrial
Commercial
C2VCCL=1.1V
C3VCCL=1.1V
C4VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3VCCL=1.1V
I4VCCL=1.1V
VCCL=1.1V
I4L
VCCL=0.9V
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
I/O Standard
Clock
GCLK
LVDS
tsuth
-1.2461.3800.822-0.548-1.2461.3800.822-0.548-1.2461.3800.822-0.548-1.0511.1781.007-0.740-1.0511.1781.007-0.740-1.0601.1870.998-0.731-1.0601.1870.998-0.731-1.0741.2010.984-0.717
-1.3081.4580.846-0.552-1.3081.4580.846-0.552-1.3081.4580.846-0.552-1.1231.2641.021-0.736-1.1231.2641.021-0.736-1.1351.2761.009-0.724-1.1351.2761.009-0.724-1.1471.2880.997-0.712
-1.5771.8321.911-1.422-1.5771.8321.911-1.422-1.5771.8321.911-1.422-1.7071.9261.776-1.321-1.7071.9261.776-1.321-1.7161.9351.767-1.312-1.7161.9351.767-1.312-1.7251.9441.754-1.300
-1.488-1.656-1.595-2.046-1.456-1.615-1.558-2.0871.7582.121
1.9502.309
1.8782.193
2.3322.091
1.7382.181
1.9202.377
1.8532.260
2.3742.149
GCLK tsuPLLthGCLK
tsuth
-1.604-1.736-1.650-1.536-1.651-1.790-1.702-1.588-1.488-1.656-1.595-2.046-1.456-1.615-1.558-2.0871.7582.121
1.9502.309
1.8782.193
2.3322.091
1.7382.181
1.9202.377
1.8532.260
2.3742.149
MINI-LVDS
GCLK tsuPLLthGCLK
tsuth
-1.604-1.736-1.650-1.536-1.651-1.790-1.702-1.588-1.488-1.656-1.595-2.046-1.456-1.615-1.558-2.0871.7582.121
1.9502.309
1.8782.193
2.3322.091
1.7382.181
1.9202.377
1.8532.260
2.3742.149
RSDS
GCLK tsuPLLthGCLK
tsuth
-1.604-1.736-1.650-1.536-1.651-1.790-1.702-1.588-1.717-1.845-1.779-2.225-1.727-1.852-1.790-2.2711.9411.887
2.0902.110
2.0131.999
2.4621.902
1.9601.904
2.1052.130
2.0332.018
2.5091.955
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK tsuPLLthGCLK
tsuth
-1.415-1.586-1.505-1.396-1.423-1.595-1.512-1.443-1.717-1.845-1.779-2.225-1.727-1.852-1.790-2.2711.9411.887
2.0902.110
2.0131.999
2.4621.902
1.9601.904
2.1052.130
2.0332.018
2.5091.955
GCLK tsuPLLthGCLK
tsuth
-1.415-1.586-1.505-1.396-1.423-1.595-1.512-1.443-1.727-1.861-1.795-2.241-1.736-1.868-1.806-2.2871.9511.877
2.1062.094
2.0291.983
2.4781.886
1.9691.895
2.1212.114
2.0492.002
2.5251.939
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK tsuPLLthGCLK
tsuth
-1.405-1.570-1.489-1.380-1.414-1.579-1.496-1.427-1.727-1.861-1.795-2.241-1.736-1.868-1.806-2.2871.9511.877
2.1062.094
2.0291.983
2.4781.886
1.9691.895
2.1212.114
2.0492.002
2.5251.939
GCLK tsuPLLth
DIFFERENTIAL
1.8-V
HSTL CLASS I
-1.405-1.570-1.489-1.380-1.414-1.579-1.496-1.427-1.737-1.879-1.813-2.259-1.747-1.885-1.823-2.3041.9611.867
2.1242.076
2.0471.965
2.4961.868
1.9801.884
2.1382.097
2.0661.985
2.5421.922
GCLK
tsuth
GCLK tsuPLLth
-1.395-1.552-1.471-1.362-1.403-1.562-1.479-1.410
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching CharacteristicsI/O Timing
Table1–99 specifies EP3SL340 Column Pins Output Timing parameters for differential I/O standards.
Table1–99. EP3SL340 Column Pins output Timing Parameters (Part 1 of 4)
ParameterI/O Standard
Current StrengthFast ModelIndustrialCommercial
C2VCCL=1.1V
C3VCCL=1.1V
C4VCCL=1.1V
VCCL=1.1V
C4L
VCCL=0.9V
I3VCCL=1.1V
I4VCCL=1.1V
VCCL=1.1V
I4LVCCL=0.9V
Units
ClockGCLK
tcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotcotco
3.4381.4273.4341.4233.4381.4273.4341.4233.4381.4273.4341.4233.4651.4543.4551.4443.4551.4443.4481.4373.4471.4363.4691.458
3.7001.6063.7031.6093.7001.6063.7031.6093.7001.6063.7031.6093.7331.6393.7231.6293.7231.6293.7171.6233.7151.6213.7371.643
5.4155.6076.1435.9916.3995.7396.2746.1226.4752.0892.1812.4062.4072.4752.2872.5112.5142.4595.4625.6626.2056.0536.4615.7986.3406.1886.5412.1362.2362.4682.4692.5372.3462.5772.5802.5255.4155.6076.1435.9916.3995.7396.2746.1226.4752.0892.1812.4062.4072.4752.2872.5112.5142.4595.4625.6626.2056.0536.4615.7986.3406.1886.5412.1362.2362.4682.4692.5372.3462.5772.5802.5255.4155.6076.1435.9916.3995.7396.2746.1226.4752.0892.1812.4062.4072.4752.2872.5112.5142.4595.4625.6626.2056.0536.4615.7986.3406.1886.5412.1362.2362.4682.4692.5372.3462.5772.5802.5255.4865.6856.2276.0756.4835.8196.3606.2086.5612.1602.2592.4902.4912.5592.3672.5972.6002.5455.4765.6746.2176.0656.4735.8086.3506.1986.5512.1502.2482.4802.4812.5492.3562.5872.5902.5355.4795.6786.2216.0696.4775.8136.3556.2036.5562.1532.2522.4842.4852.5532.3612.5922.5952.5405.4725.6726.2156.0636.4715.8066.3496.1976.5502.1462.2462.4782.4792.5472.3542.5862.5892.5345.4695.6696.2126.0606.4685.8036.3456.1936.5462.1432.2432.4752.4762.5442.3512.5822.5852.5305.4905.6896.2316.0796.4875.8236.3656.2136.5662.1642.2632.4942.4952.5632.3712.6022.6052.550
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
LVDS_E_1R—
GCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLLGCLKGCLK PLL
LVDS_E_3R—
MINI-LVDS_E_1RMINI-LVDS_E_3R
—
—
RSDS_E_1R—
RSDS_E_3R—
4mA
6mA
DIFFERENTIAL 1.2-V HSTL CLASS I
8mA
10mA
12mA
DIFFERENTIAL
16mA1.2-V HSTL
CLASSII
Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S20F672C6N中文规格书 - 图文
