Chapter 2: XPHY Architecture
Table 22: Register Description (TRISTATE_ODLY) (cont'd)
TRISTATE_ODLY
Bits
[13]
ADDR: 0x0a
Name
tristate_crse
AccessType
wo
Reset Value
0x0
Description
Along with tristate_dec and tristate_inc,determines how tristate_dly will change.
{tristate_inc, tristate_dec, tristate_crse}:000, 001, 110, 111: This allows for tristate_dlyto be written to.
100: Increment tristate_dly by one tap. Wraparound to 0x0 will happen when thisincrement occurs at tristate_dly = 0x1ff010: Decrement tristate_dly by one tap. Wraparound to 0x1ff will happen when thisdecrement occurs at tristate_dly = 0x0101: Increment tristate_dly by
INCDEC_CRSE.incdec_crse. When tristate_dlyis close to 0x1ff, this increment may wrap itaround to above 0x0
011: Decrement tristate_dly by
INCDEC_CRSE.incdec_crse. When tristate_dlyis close to 0x0, this decrement may wrap itaround to below 0x1ff
[14][15]
wowo
0x00x0
tristate_dectristate_inc
Tristate NIBBLESLICE delay decrement. See thedescription for tristate_crse.
Tristate NIBBLESLICE delay increment. See thedescription for tristate_crse.
Table 23: Register Description (ODLY0)
ODLY0
Bits
[8:0]
ADDR: 0x0b
Name
odly0_dly
AccessType
rw
Reset Value
0x0
Description
NIBBLESLICE[0] output delay value.
Reading odly0_dly returns the output delay valuein NIBBLESLICE[0], similar to reading
CNTVALUEOUT[8:0] from the PL. See odly0_crsefor the different ways to update odly0_dly.Reserved
[12:9]RESERVED
AM010 (v1.2) April 2, 2024
Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-5CS144I中文规格书
