DSP应用技术作业
XINTF的配置主要是读写时序： 读时序：
tXRDLEAD = tACE - tDOE
tXRDACTIVE = tRC + tOHA – tHZOE – (tAA – tDOE) tXRDTRAIL = tHZCE - tHZOE
// Zone read timing（tc=6.67ns）
XintfRegs.XTIMING6.bit.XRDLEAD = ; XintfRegs.XTIMING6.bit.XRDACTIVE = ;
XintfRegs.XTIMING6.bit.XRDTRAIL = ; 写时序： tXWRDLEAD
tXWRACTIVE = tPBW1 tXWRTRAIL
// Zone write timing（tc=6.67ns）
XintfRegs.XTIMING6.bit.XWRLEAD =; XintfRegs.XTIMING6.bit.XWRACTIVE =;
XintfRegs.XTIMING6.bit.XWRTRAIL =;
但是具体的配置方案暂时没有更好地想法，这里的更加优化指的是读写时间更短吗？还是什么其他的指标呢？这里不甚清楚。
6
DSP应用技术作业
作业五：
根据“Example_ADC”中实验内容，打开程序LAB11_main.c及相关头文件，阅读程序段落。
1.摘录与ePWM模块设置相关的程序语句；
（1）程序LAB11_main.c的void InitEPwm1Parameters(void)相关的配置代码: void InitEPwm1Parameters(void) {
// InitEPwm1Gpio();
// Disable TBCLK within the ePWM EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; //停止epwm模块内部的时间基准时钟 EDIS;
// TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)=150/(6*1)=25
EPwm1Regs.TBCTL.bit.HSPCLKDIV =0x03; //高速时间基准时钟预分频为两倍
EPwm1Regs.TBCTL.bit.CLKDIV = 0x00; //时间基准时钟预分频位 等于0即1分频 // Set Period for EPWM1
EPwm1Regs.TBPRD = 208;
//设定时间基准器计数器的周期208-fs 20kHz,139-fs 30kHz 149--27.9kHz T(PWM1)=TBCLK/(TBPRD*2*3)=25/(208*3*2) = 0.02MHz , 20KHz
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; //增减计数模式 // Setup Compare A = 2 TBCLK counts
EPwm1Regs.CMPA.half.CMPA = 2; //计数比较寄存器A CMPA当前工作的CMPA的值不断和时间基准计数器TBCTR比较 // Phase is 0 for Synchronization Event
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; //TBCTR不装载相位寄存器TBPHS的值 // Clear TB counter
EPwm1Regs.TBCTR = 0x0000;//事件基准计数寄存器TBCTR读取写到其中的TBCTR的值清除
// Phase loading disabled
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;//禁止TBCTR对TBPHS的装载 // Enable the TBCTL Shadow
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;//TBCTR装载其映射寄存器的值 // Disable EPWMxSYNCO signal
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; //禁用EPWMxSYNCO signal // CMPA Register operating mode, 0 means operates as a double buffer, all writes via the CUP access the shadow register
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;//映射模式，双缓冲模式，所有CPU写操作将访问映射寄存器
// Active CMPA Load From Shadow Select Mode when CTR=0
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero // Set actions
// Force EPWMA output high when the counter equals the active CMPA register and the counter is incrementing
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;//计数递增 强制ePWMxA输出高
7
DSP应用技术作业
// Force EPWMA output low Action when the counter equals the active CMPA register and the counter is decrementing
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;//计数递减 强制ePWMxA输出低 // Dead-Band Generator Rising Edge Delay Count Register=0 // EPwm1Regs.DBRED=0;
// Dead-Band Generator Falling Edge Delay Count Register=0 // EPwm1Regs.DBFED=0;
// Enable ADC Start of SOCA Pulse
EPwm1Regs.ETSEL.bit.SOCAEN = 1; //使能ePWMxSOCA脉冲 // Select SOC from CPMA on upcount
EPwm1Regs.ETSEL.bit.SOCASEL = 2; //TBCTR=TBPRD时产生ePWMxSOCA
// Select how many selected ETSEL events need to occur before an EPWMxSOCA pulse is generated;//在第三个事件产生ePWMxSOCA脉冲 EPwm1Regs.ETPS.bit.SOCAPRD = 3;
// Enable event time-base counter equal to period (TBCTR = TBPRD)
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // TBCTR=TBPRD时产生ePWMxSOCA // Enable EPWMx_INT generation
EPwm1Regs.ETSEL.bit.INTEN = 1; //使能ePWMx_INT产生
// These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated.
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; //在第三个事件产生中断 // Enable TBCLK within the ePWM EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; EDIS; }
（2）程序LAB11_main.c的interrupt void epwm1_timer_adc_isr(void)函数相关的配置代码: interrupt void epwm1_timer_adc_isr(void) //中断函数 {
xn=AdcRegs.ADCRESULT1; *Da_out=xn;
// Reinitialize for the next ADC Sequence // Reset SEQ1
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; //复位SEQ1 // Clear INT SEQ1 bit
EPwm1Regs.ETCLR.bit.INT = 1; //清除中断标志位 // Acknowledge interrupt to PIE
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; //PIEACK-PIE ackonwledge register //中断应答 return; }
（3）程序DSP2833x_ePwm_defines.h中对某些寄存器的位的定义： // TBCTL (Time-Base Control)
//========================== // CTRMODE bits
8
DSP应用技术作业
#define TB_COUNT_UP 0x0 #define TB_COUNT_DOWN 0x1 #define TB_COUNT_UPDOWN 0x2 #define TB_FREEZE 0x3 // PHSEN bit
#define TB_DISABLE 0x0 #define TB_ENABLE 0x1 // PRDLD bit
#define TB_SHADOW 0x0 #define TB_IMMEDIATE 0x1 // SYNCOSEL bits
#define TB_SYNC_IN 0x0 #define TB_CTR_ZERO 0x1 #define TB_CTR_CMPB 0x2 #define TB_SYNC_DISABLE 0x3 // HSPCLKDIV and CLKDIV bits #define TB_DIV1 0x0 #define TB_DIV2 0x1 #define TB_DIV4 0x2 // PHSDIR bit
#define TB_DOWN 0x0 #define TB_UP 0x1
// ETSEL (Event Trigger Select)
//============================= #define ET_CTR_ZERO 0x1 #define ET_CTR_PRD 0x2 #define ET_CTRU_CMPA 0x4 #define ET_CTRD_CMPA 0x5 #define ET_CTRU_CMPB 0x6 #define ET_CTRD_CMPB 0x7
// ETPS (Event Trigger Pre-scale)
//===============================// INTPRD, SOCAPRD, SOCBPRD bits #define ET_DISABLE 0x0 #define ET_1ST 0x1 #define ET_2ND 0x2 #define ET_3RD 0x3
9
DSP应用技术作业
2.指出寄存器TBCTL与TBPRD各字段的数值及其含义；
表格 3 TBCTL Register
字段 HSPCLKDIV CLKDIV CTRMODE PHSEN PRDLD SYNCOSEL
表格 4 TBPRD Register
数值 3 0 2 0 0 3 含义 二者共同决定time-base clock预分频 TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) time-base counter mode：Up-down-count mode. Phase loading disabled. TBPRD is loaded from its shadow register when the time-base counter , TBCTR, is equal to zero. Disable EPWMxSYNCO signal. 字段 TBPRD 数值 208 含义 TB counter 的计数最大值208（增减计数下:0-208，208-0）
3.指出时间基准模块TB产生事件的频率；
首先CPU复位默认频率为150MHz, TBCTL Register中HSPCLKDIV=3，CLKDIV=0，根据TBCLK频率的计算表达式计算可得：
TBCLK = SYSCLKOUT150MHz==25MHz
HSPCLKDIV ? CLKDIV6?1f1=TBCLK25MHz==60.096kHz
208?2416又因为计数器采用增减计数模式且TBPRD Register中的计数值为208，故时间频率为：
故：时间基准模块TB产生事件的频率为60.096kHz
4.指出寄存器ETSEL和ETPS各字段的数值及其含义；
表格 5 ETSEL Register
字段 SOCAEN SOCASEL INTSEL INTEN
表格 6 ETPS Register
数值 1 2 2 1 Enable EPWMxSOCA pulse. 含义 Enable event time-base counter equal to period (TBCTR = TBPRD) Enable event time-base counter equal to period (TBCTR = TBPRD) Enable EPWMx_INT generation 字段 SOCAPRD INTPRD 数值 3 3 = 1,1 含义 Generate the EPWMxSOCA pulse on the third event: ETPS[SOCACNT] Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
5.指出ADCSOC信号的产生频率；
根据ETPS Register中相关位的设置可知，事件触发子模块在第三个事件产生一个EPWMxSOCA pulse信号，因此ADCSOC信号的产生频率：
f=f160.096kHz==20.032kHz 3310
南京理工大学DSP应用技术作业
