Timing Model
Figure5–3.Input Register Setup & Hold Timing Diagram
Input Data Delaymicro tSUmicro tHInput Clock DelayFor output timing, different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device. The
QuartusII software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for default loading conditions shown in Table5–34. Use the following equations to calculate clock pin to output pin timing for StratixII devices.
tCO from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay
txz/tzx from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay + output enable pin delay
Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the QuartusII software and the timing model in the device handbook.1.
Simulate the output driver of choice into the generalized test setup,using values from Table5–34.Record the time to VMEAS.
Simulate the output driver of choice into the actual PCB trace andload, using the appropriate IBIS model or capacitance value torepresent the load.
2.3.
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Stratix II Device Handbook, Volume 1
Timing Model
Table5–36.StratixII Performance Notes(Part 5 of6)
Resources Used
Applications
Note(1)
Performance
-3Speed Grade (2)
334.11
ALUTs
TriMatrix
DSP
Memory
Blocks
Blocks
28
36
-3Speed Grade (3)
345.66
-4Speed Grade
308.54
-5
Speed Unit Grade
276.31
MHz
Larger designs
8-bit, 1024-point,quadrant output, fourparallel FFT engines,burst, three multipliers and five adders FFTfunction
8-bit, 1024-point,quadrant output, fourparallel FFT engines,burst, four multiplierstwo adders FFTfunction
8-bit, 1024-point,quadrant output, oneparallel FFT engine,buffered burst, threemultipliers and adders FFT function8-bit, 1024-point,quadrant output, oneparallel FFT engine,buffered burst, fourmultipliers and twoadders FFT function8-bit, 1024-point,quadrant output, twoparallel FFT engines,buffered burst, threemultipliers five adders FFT function8-bit, 1024-point,quadrant output, twoparallel FFT engines,buffered burst fourmultipliers and twoadders FFT function
6850
60672848367.91349.04327.33268.24MHz
2730189387.44388.34364.56306.84MHz
25341812419.28369.66364.96307.88MHz
43583018396.51378.07340.13291.29MHz
39663024389.71398.08356.53280.74MHz
Stratix II Device Handbook, Volume 1
Timing Model
Internal Timing Parameters
See Tables5–37 through 5–42 for internal timing parameters.
Table5–37.LE_FF Internal Timing Microparameters
-3 SpeedGrade (1)Min (3)
9014962204204612612162354
37861994
SymbolParameter
-3 SpeedGrade (2)Min (3)
Max
-4 SpeedGradeMin (4)
Max
-5 SpeedGradeMin (3)
Max
Unit
Max
tSU tHtCO tCLR tPRE tCLKL tCLKHtLUTtADDER
LE register setup time before clock
LE register hold time after clockLE register clock-to-output delay
Minimum clear pulse widthMinimum preset pulse widthMinimum clock low timeMinimum clock high time
9515762214214642642162354
104
104
172172
99
5962234234234234703703703703
397650
162170354372
121 200109
62
ps ps 127
ps
273 273 820 820435712
162354
ps ps ps ps 507829
psps
Notes to Table5–37:(1)(2)(3)(4)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.
Stratix II Device Handbook, Volume 1
Document Revision History
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP2SGX30CF780C5N中文规格书 - 图文
