MEMORY存储芯片MT40A1G8SA-062EE中文规格书 - 图文

Commands

DESELECT

The DESELT (DES) command (CS# HIGH) prevents new commands from being execu-ted by the DRAM. Operations already in progress are not affected.

NO OPERATION

The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands frombeing registered during idle or wait states. Operations already in progress are not affec-ted.

ZQ CALIBRATION LONG

The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibra-tion during a power-up initialization and reset sequence (see Figure 46 (page 124)).This command may be issued at any time by the controller, depending on the systemenvironment. The ZQCL command triggers the calibration engine inside the DRAM. Af-ter calibration is achieved, the calibrated values are transferred from the calibration en-gine to the DRAM I/O, which are reflected as updated RON and ODT values.

The DRAM is allowed a timing window defined by either tZQinit or tZQoper to performa full calibration and transfer of values. When ZQCL is issued during the initializationsequence, the timing parameter tZQinit must be satisfied. When initialization is com-plete, subsequent ZQCL commands require the timing parameter tZQoper to be satis-fied.

ZQ CALIBRATION SHORT

The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibra-tions to account for small voltage and temperature variations. A shorter timing windowis provided to perform the reduced calibration and transfer of values as defined by tim-ing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RONand RTT impedance error within 64 clock cycles, assuming the maximum sensitivitiesspecified in DDR3L 34 Ohm Output Driver Sensitivity (page 59).

ACTIVATE

The ACTIVATE command is used to open (or activate) a row in a particular bank for asubsequent access. The value on the BA[2:0] inputs selects the bank, and the addressprovided on inputs A[n:0] selects the row. This row remains open (or active) for accessesuntil a PRECHARGE command is issued to that bank.

A PRECHARGE command must be issued before opening a different row in the samebank.

READ

The READ command is used to initiate a burst read access to an active row. The addressprovided on inputs A[2:0] selects the starting column address, depending on the burstlength and burst type selected (see Burst Order table for additional information). Thevalue on input A10 determines whether auto precharge is used. If auto precharge is se-lected, the row being accessed will be precharged at the end of the READ burst. If auto

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Commands

precharge is not selected, the row will remain open for subsequent accesses. The valueon input A12 (if enabled in the mode register) when the READ command is issued de-termines whether BC4 (chop) or BL8 is used. After a READ command is issued, theREAD burst may not be interrupted.

Table 68: READ Command Summary

CKEFunctionREADBL8MRS,BC4MRSBC4OTFBL8OTFREAD withautoprechargeBL8MRS,BC4MRSBC4OTFBL8OTFSymbolRDRDS4RDS8RDAPRDAPS4RDAPS8Prev.CycleHHHHHHNextBACycleCS#RAS#CAS#WE#[2:0]LLLLLLHHHHHHLLLLLLHHHHHHBABABABABABAAnRFURFURFURFURFURFUA12VLHVLHA10LLLHHHA[11,9:0]CACACACACACAWRITE

The WRITE command is used to initiate a burst write access to an active row. The valueon the BA[2:0] inputs selects the bank. The value on input A10 determines whether autoprecharge is used. The value on input A12 (if enabled in the MR) when the WRITE com-mand is issued determines whether BC4 (chop) or BL8 is used.

Input data appearing on the DQ is written to the memory array subject to the DM inputlogic level appearing coincident with the data. If a given DM signal is registered LOW,the corresponding data will be written to memory. If the DM signal is registered HIGH,the corresponding data inputs will be ignored and a WRITE will not be executed to thatbyte/column location.

Table 69: WRITE Command Summary

CKEFunctionWRITEBL8MRS,BC4MRSBC4OTFBL8OTFWRITE withautoprechargeBL8MRS,BC4MRSBC4OTFBL8OTFSymbolWRWRS4WRS8WRAPWRAPS4WRAPS8Prev.CycleHHHHHHNextBACycleCS#RAS#CAS#WE#[2:0]LLLLLLHHHHHHLLLLLLLLLLLLBABABABABABAAnRFURFURFURFURFURFUA12VLHVLHA10LLLHHHA[11,9:0]CACACACACACAPDF: 09005aef8591dc1f

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Write Leveling

Write Leveling

For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topolo-gy for the commands, addresses, control signals, and clocks. Write leveling is a schemefor the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK rela-tionship at the DRAM with a simple feedback feature provided by the DRAM. Write lev-eling is generally used as part of the initialization process, if required. For normal

DRAM operation, this feature must be disabled. This is the only DRAM operation wherethe DQS functions as an input (to capture the incoming clock) and the DQ function asoutputs (to report the state of the clock). Note that nonstandard ODT schemes are re-quired.

The memory controller using the write leveling procedure must have adjustable delaysettings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.This is accomplished when the DRAM asynchronously feeds back the CK status via theDQ bus and samples with the rising edge of DQS. The controller repeatedly delays theDQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established bythis procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that usefly-by topology by de-skewing the trace length mismatch. A conceptual timing of thisprocedure is shown in Figure 43.

Figure 43: Write Leveling Concept

T0

CK#T1

T2

T3

T4

T5

T6

T7

Source

CKDifferential DQS

CK#CKTnT0T1T2T3T4T5T6Destination

Differential DQS

DQ

00Destination

CK#CKTnT0T1T2T3T4T5T6Push DQS to capture 0–1 transitionDifferential DQS

DQ

11Don’t Care

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Write Leveling

When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQoutputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 withall other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for thelower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQSand UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on ax16 enable each byte lane to be leveled independently.

The write leveling mode register interacts with other mode registers to correctly config-ure the write leveling functionality. Besides using MR1[7] to disable/enable write level-ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burstlength, and so forth need to be selected as well. This interaction is shown in Table 71. Itshould also be noted that when the outputs are enabled during write leveling mode, theDQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during writeleveling mode, only the DQS strobe terminations are activated and deactivated via theODT ball. The DQ remain disabled and are not affected by the ODT ball.

Table 71: Write Leveling Matrix

Note 1 applies to the entire tableMR1[7]WriteLevelingDisabledEnabled(1)Disabled(1)MR1[12]OutputBuffersMR1[2, 6, 9]RTT,nomValuen/aDRAMRTT,nomDRAMODT BallDQSLowOffDQOffDRAM StateWrite leveling not enabledDQS not receiving: not terminatedPrime DQ High-Z: not terminatedOther DQ High-Z: not terminatedDQS not receiving: terminated by RTTPrime DQ High-Z: not terminatedOther DQ High-Z: not terminatedDQS receiving: not terminatedPrime DQ driving CK state: not terminatedOther DQ driving LOW: not terminatedDQS receiving: terminated by RTTPrime DQ driving CK state: not terminatedOther DQ driving LOW: not terminatedCaseNotes012See normal operations??Ω????Ω???Ω????Ω, or120ΩEnabled(0)n/aHighOn2LowOff33??Ω????Ω, or120ΩNotes:

HighOn41.Expected usage if used during write leveling: Case 1 may be used when DRAM are on a

dual-rank module and on the rank not being leveled or on any rank of a module notbeing leveled on a multislot system. Case 2 may be used when DRAM are on any rank ofa module not being leveled on a multislot system. Case 3 is generally not used. Case 4 isgenerally used when DRAM are on the rank that is being leveled.

2.Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,

and all RTT,nom values are allowed. This simulates a normal standby state to DQS.

3.Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, andonly some RTT,nom values are allowed. This simulates a normal write state to DQS.

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Write Leveling

Write Leveling Procedure

A memory controller initiates the DRAM write leveling mode by setting MR1[7] to 1, as-suming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven. During write leveling mode, only the NOP or DES commands are allowed. The memory con-troller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to 1 in the other ranks. The memory controller may assert ODT after a tMOD delay, as the DRAM will be ready to process the ODT tran-sition. ODT should be turned on prior to DQS being driven LOW by at least ODTLon delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD delay require-ment.

The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a mini-mum, ODTLon and tAON must be satisfied at least one clock prior to DQS toggling.

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